Lets get to it!

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Chip slump erases $1.3 trillion in value

A broad selloff in semiconductor stocks late last week wiped roughly $1.3 trillion from market value, with memory names Micron and Sandisk among the steepest decliners as traders rotated out of high-flying AI plays. Friday's selloff added to losses on Thursday after Broadcom’s earning calls showed that demand for their custom ASICs fell short of expectations.

Micron and Sandisk, which had rallied on AI-driven memory demand, gave back gains as investors trimmed exposure to the year’s best-performing chip trades. Nvidia, AMD, and Broadcom also closed lower in the session. Jensen calls this a great buying opportunity.

(via Reuters)

Vik: It looks the market’s exuberance is finally cooling off, but such short drawdowns are not indicative of anything long term. There is some concern that companies are getting sticker shock at their AI bills. We will have to wait and see if this materially affects token spend, whether Anthropic’s steep ARR ascent will be curtailed, and CapEx spending levels off. Those are signs to watch for.

Austin: Not investment advice; agree that this feels like one of those opportunities where nothing has materially changed about AI infra demand or supply.

Nvidia, SK Hynix Sign Multi-Year Memory Pact

SK hynix and Nvidia announced a multi-year technology partnership to co-develop next-generation memory for Nvidia’s AI platforms, unveiled in Seoul by SK Group Chairman Chey Tae-won and Nvidia CEO Jensen Huang. The agreement covers memory for Nvidia’s Vera Rubin, Vera CPU, RTX Spark, and Jetson Thor platforms, and includes SK hynix adopting Nvidia’s Omniverse and CUDA-X software across its fabs. The announcement did not specify HBM allocation, exclusivity terms, or supply commitments. Huang separately flagged a prolonged chip shortage during the briefing.

(via Nvidia news)

Vik: I personally do not see the demand for memory leveling off. Co-development efforts are strong signals that memory remains an important part of AI. There is no alternative in the near horizon given how AI works.

Austin: Edge is going to continue to demand more memory too. I’m convinced local token generators will be necessary, yet the biggest complaint is that local machines (whether laptop, desktop, or even air-cooled on-premises AI racks) don’t have enough memory to support useful models with big enough context. I think interesting research with memory tiers, more efficient KV caches, and so on could impact edge device memory demand as much as datacenter.

The SoCAMM Rubin Scare

Memory stocks sold off sharply after reports that NVIDIA would halve CPU-side SOCAMM (LPDDR5X) DRAM in Vera Rubin NVL72 racks—from ~55TB to ~28TB per rack—by shipping most systems with 96GB modules instead of 192GB ones. The story originated from SemiAnalysis’s institutional research note, which was widely excerpted on social media and triggered fears of weakening AI memory demand. Founder Dylan Patel quickly clarified that the note had been taken out of context, noting most people “leave out most of the content”.

The full analysis presented the change as a deliberate optimization, not a demand warning. Analysts view the move as bullish for DRAM overall. With LPDDR5X supply still extremely tight, NVIDIA’s right-sized configs ease bottlenecks, cut ~$800K per-rack costs, improve TCO, and allow more Rubin systems to ship—reflecting smart supply-chain management amid strong AI-driven demand.

Vik: This is not the first time social media has taken institutional reports out of context, but this is also the danger of providing info to a select few. PSA to think carefully about what you’re looking at and asking “why?”

Austin: This is the SemiAnalysis business model working as designed. Sell market-moving research to a select few, and snippets will leak and lose their context on the way out the door. Sell-side notes do the same thing. There are fixes, but none are as profitable or scalable as the current approach, so it will keep happening.

Funny enough, that asymmetry is really the product: if you paid for the whole note, everyone else’s out-of-context panic is your edge. You read the full thing, retail got it wrong, the dip is a buying opportunity.

The Rubin Ultra NPO Shift

Reports revealed NVIDIA’s Rubin Ultra NVL576 platform would use Near-Package Optics (NPO) for inter-rack scale-up—nearly doubling optical-engine content per GPU from ~2.25 to ~4.0 (+78%) and implying ~12M units of demand.

The story originated from FundaAI’s institutional weekly research note, which was widely circulated on social media and forums. FundaAI presented the shift as a deliberate supply-chain decision favoring modular NPO over full CPO internalization. Analysts view it as bullish for the broader optics ecosystem.

NPO preserves and expands value for specialized optical-engine makers, lasers, DSPs, and SiPh foundries—accelerating AI networking deployment and capturing more content amid exploding Rubin Ultra demand—without handing the entire interconnect stack to vertically integrated chip giants.

Vik: I personally think that NPO is a very practical near term approach. The Rubin Ultra mid-plane PCB is a monstrosity prone to problems, and going direct to co-packaged optics has its challenges at scale. There are lots of unsolved problems. NPO is the “goldilocks zone.”

Austin: Vik tweeted about this and it got >120K views! (Tweeted… posted… whatever)

Startup News

Power Goes Vertical: Lotus Microsystems Launches vStrata

Copenhagen startup Lotus Microsystems has launched vStrata, a vertical power delivery platform that moves power conversion directly beneath the processor while managing heat at the same location.

The first module, LSC0580, has taped out for unnamed “leading xPU and AI infrastructure” partners, with engineering samples scheduled to ship in Q3 2026.

Built on the company’s silicon Power Interposer Technology, Lotus claims vStrata:

• Cuts power conversion losses by more than 50%

• Achieves up to 96% point-of-load efficiency

• Handles kiloampere-class loads and transients above 10 A/ns without external capacitors

• Lowers operating temperatures by up to 25°C

• Has a roadmap to sub-1 mm thickness

The company says it is working with Tier-1 hyperscalers through an Early Access Program and will demonstrate the module at PCIM Europe (June 9-11).

Austin: I just wrote about power delivery, check it out here to get up to speed. The space is heating up.

Key Data

We love this chart. Notice how much of both optics and copper are in there?

This tiny startup was led by two legendary scientists and their hyper-disciplined hire (universally celebrated in everyday tech lore as “Employee Number One”), who in strict legal and payroll terms was actually employee number three behind the co-founders. They wanted to build semiconductor memory chips to kill off the slow, hand-wired magnetic cores dominating the tech industry. Their early backer, Arthur Rock, had so much faith in the founders’ reputations that he famously raised the first tranche of their $2.5 million in under two days — with no formal business plan in hand, just a page-and-a-half flyer.

However, the team hit an immediate branding crisis. Their initial instinct was to simply name the enterprise after the surnames of its two iconic co-founders. But during their very first strategy meeting, they noticed a fatal phonetic flaw.

Because of the specific combination of their last names, saying the company name out loud created a terrible homophone. To anyone working in electronics, their corporate identity sounded exactly like an announcement for an increase in unwanted signal interference - the exact type of chaotic, data-ruining disturbance that hardware engineers spend their entire lives trying to eliminate. They quickly abandoned it.

After hiding under the sterile placeholder NM Electronics for a few weeks, they eventually settled on a slick portmanteau. In another twist of irony, they discovered the name was already legally trademarked by a Midwestern hotel chain, forcing the founders to shell out $15,000 just to buy the rights to their own identity.

Question: By working out the phonetic disaster that the founders narrowly avoided, name this computing giant whose first shipped product was actually a tiny 64-bit memory chip.

Pictures of the founders in no particular order.

SPOILER ALERT: ANSWER BELOW

He would never hold a position higher than technician, until a doctorate arrived in 1938 — four years before his death, too late to change anything. By every bureaucratic measure, he was nobody. And yet.

While fiddling with carborundum crystal detectors used in early radio receivers, Losev noticed that passing a direct current through the junction produced a faint, cold light. Henry Round had seen something similar in 1907 and moved on. Losev stayed. He isolated the phenomenon, ruled out heat and chemical reaction, and correctly identified it as a quantum mechanical effect: the inverse of the photoelectric effect. He called it a “light relay,” patented it, and predicted it would replace incandescent bulbs in high-speed optical communications. We call it an LED. It took until April 2007, in Nature Photonics, for the academic world to formally credit him. In a 1951 Physical Review paper that cited his work, his name was misspelled as “Lossew.”

The LED was not even his main act.

Losev had discovered something stranger in zincite crystals: negative resistance. Press a fine wire against the crystal at exactly the right point, apply a DC bias, and the material would amplify a radio signal. Current decreased as voltage increased, defying Ohm’s Law in a way that could make the crystal oscillate and amplify.

By 1924, he was building fully functional solid-state radios. Hugo Gernsback — editor of Radio News and later the man who coined the term “scientifiction,” giving science fiction its name — devoted a feature to the device and declared: “It is now possible to do anything and everything with a crystal that can be done with a vacuum tube.” He named it the Crystodyne. But Crystodyne was too finicky to scale. Losev abandoned the research after a decade. Negative resistance in diodes was independently rediscovered only in 1957, in the tunnel diode.

Meanwhile, the Soviet system had its own way of handling a man like Losev who was born to a retired Tsarist Army captain. His class background blocked every formal academic path. He received a doctorate from the Ioffe Physical-Technical Institute in 1938 only because the institution waived the thesis requirement entirely — a rare acknowledgment that his published work rendered the formality moot. By then, he had 43 papers and 16 author’s certificates for his discoveries.

When the Siege of Leningrad began, Losev refused to leave his equipment. He died of starvation on 22 January 1942. He was 38. Shortly before his death, he had mailed a manuscript describing a new three-electrode semiconductor device to Physical Review. The paper was lost in the wartime Atlantic. Five years later, Shockley, Bardeen, and Brattain invented the transistor at Bell Labs — independently, without knowledge of Losev’s work — and the world called it a discovery.

The semiconductor industry has always had this quality: the difference between a pioneer and a founder is often just access to materials, capital, and time. Losev had the ideas and none of the rest.

Let’s get to it.

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TSMC sees AI chip demand visibility through 2030

TSMC Chairman and CEO C.C. Wei told shareholders at the company’s annual meeting on Thursday that order visibility now extends to 2030, citing sustained AI-related demand and supporting a mid-30% year-on-year revenue growth target for the year. Wei said TSMC has purchased ASML’s High-NA EUV lithography tools but has not yet deployed them for mass production, and confirmed a pilot line for CoPoS advanced packaging with volume production two to three years out. He said TSMC would avoid aggressive price hikes of the kind seen in memory chips, warned of potential memory supply shortages, and dismissed competitive threats from mainland Chinese foundries and Elon Musk’s planned TeraFab. (@dnystedt via UDN)

Austin: I wonder if anything TSMC sees in that order visibility through 2030 gives it enough confidence to further increase fab expansion plans?

Vik: There was also some banter on X about how Gavin Baker called TSMC management “tough, flinty, disciplined” (and not “stubborn”)

Nvidia clears all three memory makers for HBM4

Nvidia has qualified HBM4 from Samsung, SK Hynix, and Micron for its upcoming Vera Rubin platform, Bloomberg reported, completing approval across the memory industry’s big three suppliers. The qualification covers next-generation high-bandwidth memory destined for Nvidia’s Rubin GPU systems. The news landed alongside conflicting signals on allocation: one analyst cut Micron’s projected Nvidia HBM4 supply forecast to zero, sending Micron shares lower, even as all three vendors now hold qualified status. (Bloomberg)

Vik: Classic example of how everything is not a zero sum game. All three memory makers can win, and they did. All three of them are $1T companies today.

AAOI notes a shift in optical transceivers

800G is now the baseline for serious AI infrastructure builds, and 1.6T is moving from roadmap to production volume. Industry projections put 800G+ transceiver shipments at ~63M units in 2026, up from ~24M in 2025. OSFP has settled as the dominant form factor for 1.6T. A few more points:

• 800G supply could tighten as manufacturing attention shifts toward 1.6T

• Optical qualification needs to run in parallel with GPU procurement, not after it; misaligned timelines are a real operational risk

• Vertical integration (in-house laser fab) is increasingly a supply chain differentiator for vendors

AOI is pitching U.S.-based manufacturing scale and in-house laser production as advantages for customers with TAA requirements. The market numbers and supply tightening narrative both serve their sales case, so treat specifics as directional.

(Via Applied Optoelectronics)

Vik: Someone told me at Computex that some infra builders are even choosing to skip 800G and go straight to 1.6T. Unverified, but plausible, given how fast things are moving.

SK Hynix DRAM Expansion Plan

SK Hynix is targeting ~1 million DRAM wafers/month by 2030-2031, up from ~550,000 today. The expansion is centered on the Yongin cluster, where the first fab will be divided into six cleanrooms adding 60,000 wafers every six months starting February 2027, totaling 360,000 wafers by H1 2030. M15X in Cheongju adds another ~80,000 wafers/month by next year.

The plan carries more weight than usual because SK Group Chairman Chey Tae-won publicly outlined the capacity doubling target at Computex himself. His comments also signaled willingness to expand through short-term price weakness, which is the more interesting signal for the memory market.

(via The Elec)

Vik: And you think memory has peaked? Hmm. Not financial advice, but we really cannot live without more memory in this AI day and age.

Quick Hits

Computing

• Indian startup Netrasemi brings up its flagship A2000 edge AI chip and begins supplying engineering samples plus development boards to customers, kicking off the evaluation phase. (EE Times)

• Hon Hai revenue rose 34% in the April to May period, underscoring demand for the Nvidia Corp. servers essential to AI infrastructure. Hon Hai — a key assembler of servers that house Nvidia accelerators — has said it expects business to expand substantially in 2026. (Bloomberg)

Power

• JEDEC publishes two new guideline documents covering silicon carbide (SiC) power semiconductors, aimed at supporting growing reliability requirements for SiC-based power electronics applications. (EE News Europe)

Hiring & Layoffs

• US employers announced 83,387 planned layoffs in April, up 38% month-over-month, with AI cited as the single largest stated reason for the workforce cuts. (EE News Europe)

Eye Candy

Intel publishes a TEM image of its 18A node showing the nanosheet transistors and PowerVia backside-power architecture patterning, with engineers calling the technology a game changer. (@lithos_graphein)

Watch the full video about Intel 18A.

Be sure to check out the Semi Doped podcast on YouTube or your favorite podcast player!

Broadcom AI chip forecast misses estimates

Broadcom reported Q2 FY26 revenue of $22.19 billion, up 48% year-over-year and 15% quarter-over-quarter, with adjusted earnings of $2.44 per share versus a $2.39 consensus estimate. Shares fell in after-hours trading after the company’s AI chip sales forecast came in below Wall Street expectations and management reiterated, rather than raised, its $100 billion-plus 2027 revenue target. On the earnings call, CEO Hock Tan said Google is diversifying away from Broadcom for custom silicon. The company’s market capitalization stands near $2 trillion, compared with roughly $5.2 trillion for Nvidia. (Reuters)

Vik: Hock admitted that Customer-Owned Tooling (CoT — where customers own the chip design process) is real, and some share of custom ASIC design is bound to shift away from them. Broadcom’s self proclaimed silicon prowess is starting to show cracks when others execute just as well.

TSMC reaffirms 30%-plus 2025 revenue growth

At its annual shareholders’ meeting, TSMC Chairman and CEO C.C. Wei reiterated the foundry’s forecast for full-year revenue growth above 30%, citing AI demand shifting from generative and Q&A models toward agentic and command-execution workloads. Wei said chip supply will fall short of AI-fueled demand for years and indicated no slowdown in capital expenditure. He also confirmed that TSMC’s CoPoS advanced packaging technology is running on a pilot production line, with volume expected to ramp significantly over the next two to three years. Wei added that the company is expanding mature-node capacity and signaled interest in higher chip prices. (Bloomberg)

Stanford shrinks 2D nanoribbon transistors to 15 nm

Researchers from Stanford, Chalmers University of Technology, HORIBA Scientific, and SLAC published “Scaling nanoribbon transistors with monolayer transition metal dichalcogenides,” demonstrating monolayer and bilayer molybdenum disulfide nanoribbon transistors scaled down to 15 nm channel widths. The devices showed both n- and p-type operation and maintained on/off ratios of 10^6, the highest reported for similar dimensions. The team reported improved mobility and threshold-voltage stability at narrower widths, which the authors attribute to reduced edge scattering and depletion alongside stronger electrostatic control. Two-dimensional semiconductors provide the thinnest possible channel layer, but good performance had previously been limited to micrometer-wide channels. (Nature)

Austin: from Professor Pop on LinkedIn:

Quick Hits

Memory

• JEDEC’s LPDDR6 roadmap adds data-center-oriented features, including higher bandwidth and reliability extensions, as LPDDR gains traction inside AI servers alongside HBM and DDR memory. (EE Times)

Semicap

• Semiconductor laser annealing is gaining broader adoption beyond logic, expanding into SiC power devices and 400-layer NAND processes where conventional thermal treatment falls short. (@jukan05))

Infrastructure

• Xnrgy, an AI data center cooling and power infrastructure parts maker, is exploring a sale that could value the company at roughly $10 billion. (Bloomberg Tech)

Foundry

• InchFab is selling $10 million mini fabs to pharmaceutical maker Roche and universities, aiming to democratize chipmaking with compact lithography and processing tools for non-traditional buyers. (EE Times)

Packaging

• Genesem completed development of vacuum and flip mounters for advanced HBM packaging, signaling rising orders as HBM3E and HBM4 ramps draw fresh demand for assembly equipment. (The Elec)

Networking

• Cisco positioned its Silicon One platform for secure agentic-AI networking, emphasizing in-band telemetry, segmentation, and traffic-isolation features built for AI training and inference fabrics. (Cisco Blogs)

Consumer

• Mid- and low-end handset vendors are eyeing exits from the smartphone market as elevated memory prices, war-related component shortages, and weak demand pressure margins, Counterpoint warned. (Light Reading)

That’s it for today!

Be sure to check out the Semi Doped podcast on YouTube or your favorite podcast player!

Nvidia opens NVLink Fusion to photonics partners

Nvidia announced at GTC Taipei 2026 that its NVLink Fusion ecosystem will extend to photonic interconnects, with Lightmatter and Ayar Labs joining as co-packaged optics partners. Lightmatter is contributing its Passage photonic interconnects and Guide laser sources, while Ayar Labs is making its CPO products optically and electrically compatible with Nvidia’s optical and SerDes technologies for rack-scale AI infrastructure. (Ayar, Lightmatter)

Shares of optical suppliers Lumentum, Coherent, and Corning rose sharply following CEO Jensen Huang’s remarks:

Jensen: We should use copper as much as we can, for as long as we can, but copper has its limits. The right strategy is to scale up with copper as long as you can. After that you scale up further with optics, you scale out with optics and you scale across with optics. So you use optics wherever you must, you use copper wherever you can.

My take:

Austin: Nothing new was said. A near-term interpretation of Jensen’s comments: scale-up inside the rack using copper, extended scale up between neighbor racks using optics, scale out and across with optics. Where the scale up TAM truly grows for optical names is when scale up inside the same rack moves optical. That will come, but not nearly as soon as the rhetoric makes it seem. Read more about timing here.

Windows laptop with beefy GPU

Microsoft and Nvidia introduced RTX Spark, an Nvidia processor for thin-and-light Windows PCs with 1 petaflop of AI performance, up to 6,144 Blackwell RTX cores, up to 20 Arm CPU cores, and up to 128GB of unified memory. The pitch is the on-device agents: 128GB of unified memory runs frontier-class models and agent tools locally (GitHub Copilot, Claude Code, Cursor, ComfyUI, TensorRT), with a new Windows OpenShell runtime to sandbox them. Beyond the laptop, the two scaled Windows to the DGX Station deskside box (GB300 Grace Blackwell Ultra, 748GB coherent memory, 20 petaflops FP4, trillion-parameter models), due later in 2026. First laptops to ship this fall include the Surface Laptop Ultra, ASUS ProArt P16, Dell XPS 16 Creator Edition, HP OmniBook, Lenovo Yoga Pro 9n, and MSI Prestige. (Microsoft Build, Windows).

Austin: I’m actively migrating some of my own workloads to my local token generator, a Framework AMD Ryzen Max+ 395. It’s my always-on agent computer on my desk. Note that it has 128 GB of memory too, which is actually enough in my experience for many of my simple agentic tasks. Sure, there’s a cap to context length and token generation speed. But I have a lot of background tasks where that’s just fine. The memory and compute won’t be the barrier to local agentic AI imo, rather the user experience and consumer awareness will be. That’s where Microsoft has a big opportunity to help.

Alphabet wants $80 billion

Alphabet is raising $80 billion in equity to fund AI compute: about $30 billion underwritten, $40 billion via an at-the-market program, and a $10 billion private placement from Berkshire Hathaway. The reaction was muted, down about 2% premarket, partly because nearly 40% of the raise is earmarked for employee equity-tax obligations rather than direct capex. (WSJ)

Austin: Ben Thompson has a good read on this here: The Google Capital Company

Quick Hits

Semicap

• Koh Young Technology said its semiconductor packaging inspection equipment sales jumped 79%, driven by surging demand from AI server packaging programs. (The Elec)

Storage

• Chinese NAND makers have reached market share comparable to Micron and SanDisk, narrowing the gap with traditional incumbents, per market data shared by analysts. (@jukan05)

• Sandisk announced a plan to shield budget consumers from the broad memory price surge by offering value-tier storage products despite rising NAND and DRAM costs. (bgr.com)

Infrastructure

• A CoreWeave-tied data center entity raised $900 million via a junk-bond sale, adding to financing stacks supporting continued GPU-cloud capacity expansion. (Bloomberg.com)

Networking

• Astera Labs is expanding its Taiwan operations to accelerate global AI infrastructure buildout, deepening its presence in the island’s hardware design and supply ecosystem. (GlobeNewswire, Stock Titan)

Cool Stuff

Fourty minute video from TechInsights on 18A, per on X.

That’s it for today. Austin’s on his way home from Computex; flight through Toyko was cancelled due to Typhoon Jangmi, hope our Japanese friends are all doing ok!

Be sure to check out the Semi Doped podcast on YouTube or your favorite podcast player!

Marvell Keynote at Computex

The whole talk was about how Marvell is at the forefront of optical connectivity. CEO Matt Murphy showed off their CPO switch, and spoke about how the copper wall is moving into the rack such that only very short interconnects are still in copper. In our opinion, this is overly optimistic and in-rack copper scale up is here to stay for the time being. Not to say optics is not important; both will coexist for at least a few more years. Marvell also announced their 102.4Tbps Teralynx switch.

Then Jensen showed up and called Marvell the next trillion dollar company. I guess that has stirred stock? Hmm, whatever. Here’s a fun video of him running in.

Intel ramps 18A, launches Panther Lake and Arc G3

Intel CEO Lip-Bu Tan announced at Computex 2026 that the company’s 18A process is now at full scale, with Core Ultra 3, Core 3, Clearwater Forest, and Xeon 6+ in production on the node. More than 300 Panther Lake devices are shipping, and Wildcat Lake has secured 70 designs. The keynote introduced the Arc G3 discrete GPU and highlighted 130+ edge devices across 4,000+ partners.

Austin attended Intel keynote and has better insights, but is too jet lagged right now to write on this update. We’ll likely do a full podcast episode on Computex next week, so stay tuned.

Oracle, ByteDance adopt Arm data-center CPUs

Arm said Tuesday at Computex that Oracle Cloud Infrastructure and ByteDance are using its data-center CPUs, joining a growing roster of Arm AGI CPU ecosystem customers that includes Cerebras, Cloudflare, F5, Meta, OpenAI, Positron, Rebellions, SAP, SK Telecom and Verda. Oracle cited momentum with Arm-based infrastructure across cloud-native workloads, naming Uber among the customers running on its Arm servers. The announcement builds on commitments Arm outlined at its Arm Everywhere event on March 24, where the company said agentic AI workloads would drive higher CPU demand in the data center.

(Arm newsroom)

Quick Hits

• NVIDIA Jetson Brings Agentic AI to the Physical World (Nvidia)

• AWS announces general availability of OpenAI GPT-5.5, GPT-5.4, and Codex models on Amazon Bedrock, expanding hosted third-party model offerings for enterprise customers. (AWS Blogs)

• GoPro warns of going-concern risk amid the AI-fueled memory crunch, citing pricing pressure from constrained DRAM and NAND supply on its action-camera margins. (Bloomberg Tech)

• Nextpower acquires battery energy storage specialist Prevalon Energy, expanding beyond solar power into the utility-scale BESS market increasingly tied to AI data center build-outs. (EE News Europe)

In Rack Optical Scale Up

There was this really cool looking rack that shows what optical scale up looks like. All those plugs in blue are ELSFP laser modules, and all the yellow cables are optical fibers going into a switch. Beautiful 🤌🏽

Be sure to check out the Semi Doped podcast on YouTube or your favorite podcast player!

Dell, CoreWeave Deploy First Vera Rubin NVL72

Dell Technologies and CoreWeave have completed the first deployment of NVIDIA’s Vera Rubin VR200 NVL72 rack-scale system, with Michael Dell announcing the milestone on May 30, 2026. The installation passed L11 diagnostics, a full rack-scale validation test covering all components in the integrated system. According to SemiAnalysis, CoreWeave and Dell are the first cloud provider to announce a Rubin NVL72 with fully passing L11 diags, with next steps including multi-rack burn-in and software-level bringup using frameworks such as sglang, vLLM, and Dynamo.

Vik: Always nice to see hardware hooked up, even if the cable management is sketch. Those cable whips in the back are cool. I got the chance to hold one at Computex 2026, and they are HEAVY!

Nvidia, Microsoft to unveil first Nvidia-powered Windows PCs

Nvidia and Microsoft are expected to unveil the first Windows PCs powered by Nvidia chips next week, according to an Axios report cited by Reuters. The lineup is expected to include Microsoft Surface models alongside devices from other manufacturers. Dell is preparing an embargoed XPS launch using Nvidia’s N1X platform, which pairs an Arm-based CPU with a Blackwell integrated GPU, with Lenovo and ASUS lined up as additional first-tier OEM partners. The rollout marks Nvidia’s entry into the Windows-on-Arm PC segment currently served by Qualcomm, AMD, and Intel silicon.

Vik: Sick burn by Dylan Patel on X. 🤣

NVIDIA Computex 2026 Keynote

We heard from people who were in the keynote firsthand that the whole thing was boring. Nothing they hadn’t heard already. N1X response was also underwhelming. Vik was still on the flight and didn’t attend, and Austin was doing important day job work. Important number to note though: 1GW of compute is going to cost $80B to build.

Power Wall

Just look at all these 800V power chips at Computex. Cool!

Senefelder spent the next three years turning that moment into a working process. He called it “stone printing.” A French term won out instead, built from two Greek roots: one meaning stone, the other meaning to write.

The limestone came from quarries in a small Bavarian town roughly halfway between Nuremberg and Munich. Decades later, workers cutting that same stone for the printing trade split open a slab and found something strange pressed into both halves: a creature about 150 million years old with the feathers of a bird, but also a long bony tail and three clawed fingers on each wing. It surfaced in 1861, two years after Darwin published On the Origin of Species, and became one of the most famous fossils in science as early evidence of one kind of animal shading into another. Naturalists named it after the stone it came out of. Its species name is the exact same word as the printing process.

Now take the stone out of the story completely. The process has not touched limestone in a very long time, but the name survived, and today it describes the step that decides how small the features on a computer chip can be: printing circuit patterns onto silicon. The most advanced version uses no ink and no visible light. It fires a laser at droplets of molten tin to generate light at a wavelength of 13.5 nanometers, bounces that light off mirrors polished to near-perfect flatness.

Question: Name the process and the feathered fossil that shares its name.

The two Greek roots are lithos (stone) and graphein (to write).

SPOILER ALERT: ANSWER BELOW

There is this flooded pit on a small island outside Stockholm that used to be a quarry for quartz and feldspar - the dull stuff that glass and porcelain are made of. In 1787 a Swedish army lieutenant named Carl Axel Arrhenius, who collected rocks the way other officers collected debts, picked up a heavy black stone there and decided it was a new tungsten mineral. He was wrong. What he had actually found was a sampler plate from the bottom of the periodic table.

Over the next century, chemists kept teasing new elements out of that one rock and its relatives. Four are named directly after the village: yttrium, terbium, erbium, and ytterbium. Several more, holmium, thulium, scandium, gadolinium, and the heavy metal tantalum, were first pulled from the same minerals. For two hundred years this was pure pub-quiz material for the chemistry nerds. Then silicon started running out of road, and the toolmakers went looking in the strange middle of the periodic table for help.

Why these elements and not others? It comes down to where they keep their electrons. Ordinary silicon chemistry happens on the outside, with electrons shared politely between neighbours. Most of the Ytterby metals are lanthanides, and they tuck extra electrons into an inner shell - the 4f - that sits buried under the outer layers like a letter inside two envelopes. Shielded from the chemical traffic outside, those buried electrons keep very clean, very sharp magnetic and optical behaviour, which is exactly the sort of tidy quirk an engineer will travel a long way to use.

The surprising part is that only a few of them earned a real job in a chip, and the jobs are oddly specific.

• Yttrium is the bodyguard: when a fab etches features into a wafer it uses fluorine plasma that would chew an ordinary quartz chamber to lace, so the chambers are lined with yttrium oxide, one of the few coatings that can stand in that fire without flaking.

• Scandium is the quiet success of the group, alloyed into aluminium nitride as AlScN to make the radio-frequency filters inside 5G phones, and now a leading material for a new kind of memory.

• Erbium is the relay runner, doped into glass to amplify light at the wavelength where optical signals travel furthest, the trick behind fibre-optic telecom, and now being built straight onto silicon to move data between chips.

The strangest thing I learned is what tantalum does.

It was found at Ytterby in 1802, it is not a rare earth, and almost nobody thinks about it. Yet a thin layer of tantalum nitride lines the copper wiring on very nearly every chip made today, which makes the most anonymous element from the quarry the one you are most likely to be holding right now.

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The rest are still mostly famous for things they cannot quite do yet.

• Ytterbium makes a fine qubit, but for trapped-ion quantum computers that do not use chips at all.

• Holmium has the highest magnetic moment of any natural element and once held a single bit of data on a single atom in an IBM lab.

• Lutetium was the great hope for a sharper lithography lens that never reached production. Again, good pub trivia, but not much silicon.

The elements from that quiet ditch are not rare in the crust, only rare in concentrations worth mining, and the world now buys nearly all of them through a very small number of doors.

China mines about 70 percent of rare earths and refines close to 90 percent. The famous Bayan Obo mine in Inner Mongolia mostly yields the light ones; the heavy members of the roster come largely from clay deposits in southern China and from Myanmar. The United States has essentially one mine, Mountain Pass in California, and Australia’s Mount Weld is the main door that does not open onto China.

So the last thing I learned today: in 2025 China put export controls on seven rare earths, and several of them, yttrium, scandium, terbium, dysprosium, gadolinium and lutetium, came straight off the Ytterby list. A 250-year-old quarry, found by a man who misidentified his own rock, is now a line item in a trade war.

Is it real, or is it marketing? Vik and Austin unpack what Huawei actually announced and explain why the “EUV killer” headline gets the story backwards. EUV dead? Nope. ASML hurt? Actually, the opposite.

Things we cover:

• What the “tau scaling law” actually is, and why tau means delay

• Logic folding: stacking logic on logic via hybrid bonding

• The Kirin 2026, and doubling transistor count without shrinking

• Who can build it, and whether hybrid bonding tools can be export-controlled

• Why stacking is bullish for ASML, not bearish

• The other tau knobs: a unified memory bus and near-packaged optics

This podcast is lightly edited for clarity.

The Huawei Paper That Broke the Internet

Austin: Welcome to another Semi Doped episode. I’m Austin Lyons with Chipstrat, and with me is Vik Sekar from Vik’s Newsletter. Hey Vik, what’s up?

Vik: Yeah, how’s it going? It’s going well. It’s a nice time to chat. We usually do this later in the week — usually we record on a Thursday, but today we’re doing Tuesday. And it’s perfect, because we were actually going to talk about something else, but then there’s this paper that dropped from Huawei that said something to the effect of, we’re bypassing EUV, we’re going to be at TSMC’s 14 angstrom equivalent by 2031. And everything online all at once is hitting me in the face, saying Huawei has circumvented EUV, ASML is dead in the water, US dominance is gone in leading-edge nodes. At least that’s the sentiment I get. And considering we recorded the deep dive on lithography last week, I texted you and said, okay, can we just talk about this early this week? Because it’s so fresh in my mind, we should just do this.

Austin: Yes, yes. So this is perfect. Let’s talk about it. And in fact, it was Memorial Day in the United States yesterday, so I was hardly even online, but the internet was blowing up. So I’m glad that you texted me, I’m glad that you read it, and I look forward to learning from you through this conversation. And I will say, I wonder how the United States government — anyone in those circles, like the Commerce Department — how they’re feeling. Because of course lithography, EUV lithography, is the big geopolitical chip on the table. And I bet some of them have to be freaking out if they heard or saw on X, like, yeah, what you used for controls is now rendered useless. They also have to be like, wait a minute, is this real, or is this marketing? So that’s the goal of this — to unpack what Huawei actually announced, and whether the marketing speak and the interpretation were different than the technical paper and the technical innovations here.

Vik: Yeah, so we wrote this down in the Semi Doped newsletter — this is kind of where our first reactions go. So if you’re not signed up to that, as the listener, you should. It’s free on Substack. You should go to semidoped.com and sign up, because whatever news comes our way, we just try to write up quickly the first thought that comes to mind. Usually it’s the most natural response. But after that, I got a few questions saying, hey, what do you think of this piece of news? And I responded and said, yeah, this is really interesting that Huawei has this approach of trying to improve performance of chips overall, but without going to the fancy machines, which they can’t get a hold of because they’re all under export control.

So without much ado, I think we should first explain what the whole claim was. There’s this conference called ISCAS 2026 that I believe is being held in Shanghai this week. And He Tingbo, who is a Huawei director and the head of HiSilicon, which is the chip arm of Huawei, gave a talk. I did not hear the talk. Do you know if He Tingbo is a he or a she? Because I might totally get this wrong.

Austin: I saw a picture of a woman, so I think whoever gave the talk was a woman, I’m pretty sure.

Vik: Okay, I’m glad I asked.

What Tau Scaling Actually Is

Vik: But anyway, the point is, the whole idea is that there’s this new guiding principle called the tau scaling law. And the spiel, at least, is that it’s going to replace Moore’s law. Because over time Moore’s law has stopped scaling, and we’ve been squeaking along ever since we hit the EUV nodes below 7 nanometer. The whole idea is, okay, let’s look at something else. And this is where I actually like this framing — the tau scaling law has a much more fundamental scaling that I truly appreciate. And I need to explain why this tau thing, first of all. Tau is a measure of delay. It could be delay on the chip, it could be delay through the interconnect, it could be delay between racks, it could be delay between entire data centers, anything.

So the whole idea of going to smaller transistors was essentially to minimize this delay. The smaller you made a transistor, the lesser the delay got from the input to the output of the transistor, and that only meant it went faster. So for the longest time, the only way to make things go faster was to reduce the delay. So Huawei’s interpretation is to stop thinking about dimensions of the transistor, which they really can’t scale without EUV machines. But why not go down one further level and ask what the transistor was solving anyway? And the answer was delay.

So then the next logical question is, okay, we can’t improve the transistor delay anymore because we don’t have the machines. So where else can we improve the delay? Because it’s not like delay comes only from the chip or the GPU or the CPU or whatever it is. Delay is everywhere. Delay is in software, delay is in interconnects and how you hook up memory, what memory protocols and handshakes you do. So they were like, okay, let’s reinvent everything and think of this from a whole-system perspective. So this is what they call their tau scaling law. We will now scale down tau at the system level, not so much at the transistor level that has been done historically, but over the entire system. It could be a phone to begin with, or an entire AI data center. We are now scaling down delay.

Austin: Okay, that makes sense. So summarizing it, they’re basically saying, hey, Moore’s law is dead. And by the way, even if it’s not dead, we can’t shrink transistors anyway because we can’t get our hands on EUV tools. So if we want to continue to increase performance, and we can’t reduce the geometric footprint of each transistor, how can we increase performance? And so they zoomed out and said, well, wait a minute, maybe the geometric scaling of transistors was actually ultimately about reducing delay. And so they’re trying to reorient around tau — this time-delay, resistance-capacitance product — and say, okay, fine, we have one knob that we can’t turn, but what are all the other knobs we could turn to continue to reduce delay?

And I do like the point of not just delay at the transistor level, but extreme co-optimization, or STCO, DTCO, which we could talk about. I saw you had a tweet about this. Which is just saying, how can we look up and down the whole stack — from transistors and devices to circuits to systems to racks to interconnects to the whole data center to software on top of it — and how can we try to co-optimize amongst all of those?

Vik: Yeah. So whenever they say this is kind of a law, it’s always nice to see some equation. And I read the whole paper, actually — it’s an easy read for a paper. And they had this nice equation which says the tau of the transistor, the tau of the system, is basically the delay through the transistor, delay through the circuit, delay through the chip, and delay through the system. And what they want to do at every subsequent generation — the tau of the next generation — is the tau at this generation divided by some factor alpha, where they think that alpha factor is like 1.3x a year for mobile, and 1.5x for auto, and maybe even 10x for AI workloads. So think about that — optimizing across the system, they’re thinking they can reduce the delay by 10x for AI workloads. That is a significant improvement. And that is why they feel like they can get 1.4 nanometer-class performance by tweaking other parts of the system, not just the transistor.

Austin: Okay, so this law — most of these laws are not actual physical laws, they’re observations. So they must have had in their paper... were they showing chips that they created and measured these constants, and that’s where they’re seeing the scaling? Or where did this data come from in this empirical observation?

Logic Folding: Stacking Logic on Logic

Vik: It’s not anywhere. So they have some silicon — let’s get to that in a bit. But their optimizations were interesting, because they happen, from what I could tell, across three dimensions. The first dimension was that they just want to make transistor density more. That’s the whole thing that EUV does — EUV lets you pack in more transistors per unit area of the chip by making transistors smaller. So they stepped back and asked, okay, we can’t make transistors smaller, so how do we scale up the number of transistors in a chip? So they decided, okay, fine, we’ll just take two chips and stack them one on top of the other and hybrid bond it.

Hybrid bonding is a packaging technique that’s very interesting, because you can have millions of connections between these two logic chips. And the way it works is that you just heat them and put pressure, and they literally stick to each other. In the simplest way, that’s what hybrid bonding is. So you can have very, very fine connections that are closely spaced — the pitch between connections is something like 1.5 micron, across a massive area of a chip. Think about that. So hybrid bonding is a very fine-pitched packaging technology, which is probably the most advanced packaging technology you can get.

So that first dimension was, okay, let’s just stack two chips together. So in the space of one chip, we now get two chips. Hooray. That’s one way to get transistor density. That’s kind of cheating, because now you also use two times the silicon area, since you’ve got to sandwich two wafers together. But considering the cost of EUV, which we discussed in the last podcast episode, maybe it’s not a big deal, just saying.

Austin: Yeah, yeah, totally. Okay, so you’re saying they’ve got a chip, they can’t increase the transistor density because they’re at their fundamental limits with DUV and multi-patterning and whatnot. And historically, by the way, how the industry is kind of quote-unquote getting around Moore’s law is systems of chips. Whether you’re using chiplets or whatever — okay, well, let’s use 2.5D integration and put chips next to each other, and then we’ll have CoWoS, or interposers, connecting things. But you’re saying that Huawei said, no, wait a minute, what if, instead of putting those transistors far apart and having increased delay because now we’ve got to route between them, what if we just try to decrease the delay by stacking them in three dimensions, to increase the density, if you will, in a unit volume really.

Vik: Yeah, they call it logic folding, which is a nice name. But it’s really, if you think of it, no different, I feel, compared to what Intel Foveros is, or how AMD stacked SRAM with V-Cache. I guess it’s not technically logic-to-logic stacking when you’re talking about AMD’s V-Cache, because they put SRAM on top of a logic wafer to boost L3 cache on it. But in principle, yeah, they hybrid bonded an SRAM wafer onto a logic chip, and that’s kind of what this is all about.

So logic-to-logic stacking is not easy, right? Because how are we going to get heat out of this thing? That’s one example — thermals are quite challenging. So there are a lot of challenges to doing this stuff. And you’ve got to align it. Think about it — the connections are like 1.5 micron pitch. It’s actually ridiculously tiny. And so the alignment between the bonds needs to be perfect. And hybrid bonding itself is a crazy packaging technology, because the surfaces that you’re bonding need to be very flat and defect-free and all that. Because when you squeeze it together, if there’s a dust particle between the two of them, you know what happens — now you’ve got an open connection between the two sandwiched chips, and that’s bad. So it’s a challenging process.

That’s the whole question — does China actually have the equipment to do this? Funnily, they do, for two reasons. One, they do have this expertise, because they have been doing memory stacking for NAND at YMTC using wafer-to-wafer stacking and hybrid bonding of chips. That’s how NAND chips work — they’ve even done hundreds of layers of NAND. So they are familiar with it. But memory is a little bit of an easier problem, because memory has so much redundancy that you can route around stuff — have failovers in the memory architecture and stuff like that. So stacking is a different problem in memory than it is for logic. Stacking two GPUs on top of each other is a significantly harder problem than trying to stack 400 layers of NAND memory, you know?

Austin: Totally. So, okay, you’re saying historically stacking things is not a new concept. Even stacking logic is not necessarily a new concept. But normally when we’re stacking — let’s say logic on an interposer — that interposer is passive, so it’s not as big of a deal, you’re just routing through it. And even if you’re stacking memory on logic, that’s a little... and of course memory, and NAND and HBM, a lot of these things are already three-dimensional. So we’re already used to figuring out how to create things in three dimensions and stack them. But it is a bit of a different beast when we stack logic on top of logic, because they’re both active, they’re both powered, they’re both giving off thermals, and you have to make sure all the connections are correct. And there’s not this built-in redundancy where, if something fails, just route around it. But conceptually, to the industry, logic on logic is not a new thing that Huawei has invented.

Vik: No, it’s not, and it’s been around in principle. So that’s what makes it interesting — it’s a challenging problem, and it’s impressive that they do have silicon. It’s called the Kirin 2026. This is a mobile SoC processor, and they actually have this implemented, and they have plans to keep going in the future. The paper has all these numbers — yeah, here I have them. They’ve managed to double their transistor count, obviously by stacking. And so they kind of jump nodes, in principle. Because, we spoke about this, there is no such thing as 5 nanometers or 2 nanometers anymore, because the transistor architectures have changed. So this is just the nomenclature now anyway. So you can go to the same class node by doing other things.

Gate-all-around was one of those other things you could do to go to 2 nanometers. So Huawei’s approach is, yeah, we’ll just stack transistors and we’ll get the same transistor density. In principle, this is like CFET maybe — a complementary FET — where people were like, why should I put an NMOS and a PMOS transistor next to each other? Because for a CMOS, the complementary MOS, you require P-type and N-type transistors. What if I put them on top of each other? You can save space. So this is along the same inspired lines, not exactly the same thing. But basically, why not put a whole transistor wafer on top and stack them up like that, and you can jump generations forward. So they’ve done it, and this is very impressive engineering — all kudos to them. I’m not going to take away from their engineering achievement here. So that is the whole logic stacking aspect of it.

There are two more things that I think are very useful, but I want to get to those after you ask me this question. Yes.

Who Builds It, and Can the Tools Be Restricted?

Austin: Thank you for letting me graciously interrupt. So on the logic stacking — one of the things this reminds me of, of course, is DeepSeek, in that they could not get enough compute. They could not get enough compute and enough memory bandwidth with the chips that they were given. Allegedly — okay, maybe they did find their way to some H100s, but allegedly they had these stripped-down chips, which caused the DeepSeek team to have to innovate in other dimensions because they were constrained on one. And so they got to be the first to think deeply about other things, like, how do we offload some communication, overlap some communication and compute, do other little tricks so that we still unlock the right performance.

And so what I’m thinking about is, okay, if Huawei is constrained to not use EUV, and therefore they’re thinking about how can we reduce delay in other parts of our system — and one of them is, it’s forcing them to go to logic-to-logic stacking, maybe sooner than the rest of the industry feels that they have to. My question is, who is manufacturing it? And is this giving them an advantage in just getting more practice manufacturing logic on logic? Like, will they be able to run ahead a little bit because they are forced to build this for their customers sooner than, say, a TSMC?

Vik: Yes. This is a good question, and I’m glad you asked this now before I went on to talk about something else. Because the fact that we are stacking logic on logic has two implications. The first one is, it is entirely centered around hybrid bonding, because that is the secret sauce that allows them to increase transistor density. So you can increase the density two times. Can you stack it three times? I don’t know. Can you stack it four times? I don’t know. So what is the limit on hybrid bonding here? How many layers? That’s something I don’t know. But remember, it gets extremely difficult, because if you are stacking logic on logic, I think you would want to do die-to-wafer stacking, not wafer-to-wafer stacking, because you will get wrecked on yield. As it is, these logic chips are kind of big. And yield is such an important thing, because you don’t get all that much as people imagine, especially at the very cutting edge. But maybe 7 nanometer nodes is okay.

So that is one aspect of it — that it’s entirely based on hybrid bonding. And the question is, are they capable of it? And the answer to that is, at this point, memory-to-memory was all wafer-to-wafer — so memory stacking is all wafer-to-wafer. But logic needs die-to-wafer, and that is kind of new even to BESI and these companies that specialize in hybrid bonding. Even they have product releases that are very recent. So die-to-wafer bonding in logic chips is very cutting edge. And luckily, from what I was looking at, there is no export restriction on hybrid bonding machines. You have extremely high limitations on what you can do in EUV, but not so much on hybrid bonding machines. So that’s one thing — they do have the machines that they can do this with. And if you look at BESI’s business, 35% of all their business is actually China-based, if you see the last quarter. So that is a large fraction of their machines that actually do go to China. So I’m pretty sure they’ve stacked up on some BESI machines before they let this cat out of the bag.

Because if you already have a piece of silicon that’s stacked up and working, as in the Kirin mobile SoCs, you can believe that they have been working on this for years. This is not an overnight achievement.

Austin: So you’re saying SMIC is the manufacturer here, and they can’t get EUV machines, but they can get hybrid bonding machines, and hybrid bonding is the secret sauce here to logic stacking. So do you think that someone’s going to try to go say, now you can’t buy hybrid bonding equipment anymore?

Vik: So Huawei never said it’s SMIC, by the way — everybody assumes it is. Because it’s a reasonable assumption, and their stock went up and all that, which is cool. But I don’t think it’s SMIC who will do the stacking aspect of it either, because there are specialized people in packaging in China whose names we shouldn’t get into. I’m writing an article on Substack on this, so all those details will be on there. But there is another company that will do the hybrid bonding, because there is a whole learning curve on learning to do hybrid bonding. So there are companies who have patents just on hybrid bonding, and that is something that is not easy to do. So that’s a separate skill set. China is working on that as well.

So that’s the one important thing — it’s all hybrid bonding based. And the next question is, okay, does China have any local hybrid bonding machines? The answer is yes, they do, but I don’t think they are at the same level of sophistication there is for wafer-to-wafer bonding, for example. So that is something they still rely on BESI for. And to answer your question — yes, they can impose restrictions on it, on China, I presume. But it really comes down to, if they can get EV Group wafer-to-wafer bonding... there is a company called EV Group, which is an Austria-based company, and they are not in this axis of export restrictions that BESI is in, because BESI is a Netherlands-based company, and they’re in the same boat as ASML and stuff like that. These countries have a lot of export restrictions. But if they can do wafer-to-wafer bonding — who knows? Maybe they’re not subject to export restrictions, because Austria is not part of this thing.

Austin: Yeah. Well, okay, I did not expect that this conversation would get so much into hybrid bonding, so that’s cool. And I’m like, I need to go learn more about hybrid bonding in the market and who all the competitors are. And then two — yes, these poor European countries, they’re like, we invented something, we’re awesome at wafer-to-wafer hybrid bonding, and then they’re going to get caught up in the crossfire of geopolitics.

Why This Is Actually Good for ASML

Vik: The one thing I anticipate is, wait, if China can’t do EUV, is ASML affected by this news of tau scaling? No, because first of all, they were never buying EUV machines from ASML — they can’t. So there’s never a business to begin with. Secondly, I will argue that this is actually good for ASML. Because remember, now they have to make two wafers using deep ultraviolet — DUV — for every transistor. So they need more DUV machines, which is a positive for ASML, right?

Austin: There you go. I like it. That’s a positive spin.

Vik: Yeah, that’s a positive spin on it. So that’s the whole thing about how this whole logic thing works.

Austin: So then, really quick — logic to logic, maybe last thing. We’re talking about companies who build the die and other companies that package them. It’s kind of the front end and the back end. Of course, Intel Foundry can do both — they can make the wafers, they can also do the advanced packaging. And you mentioned Intel Foveros Direct. So can you say 10 more seconds on Foveros, and whether this is a direction that Intel Foundry could support with the logic-on-logic stacking and packaging?

Vik: Yeah, I don’t see why not. That is essentially what Intel Foveros is, as far as I understand it. And what this shows is — this is the other thing I wanted to mention, it comes to me now that you asked the question — basically, there is no reason that any US fab, like Intel or anybody else, like TSMC, shouldn’t start stacking wafers now. Because if you stack a 7 nanometer wafer and then you get tau scaling to work, imagine what will happen when you stack a 5 nanometer wafer, or a 3 nanometer process node, or a 2 nanometer process node. You’re going to leapfrog past what China can do with tau scaling.

So they may be able to catch up, but what this will do now is drive the ability to do hybrid bonding in the advanced EUV nodes — because why not? It’s not an overnight thing, it’s a very complicated thing to do. But think of it long term. If you can stack 2 nanometer node wafers, that is an amazing amount of compute in a small area. And we may get to CFET before that — maybe we don’t need it. We may do hybrid bonding of gate-all-around FETs before CFET shows up. Don’t know. Or we may hybrid bond CFET wafers together — the ultimate density move.

Austin: Totally. We should do it all, right? The front-end folks should keep working on the transistor innovations, and the packaging folks should keep improving stacking and hybrid bonding, and then slam it all together. And I do agree with your point, which is — okay, let’s say I can do a billion transistors in this little area, and now I can stack them so I get two billion. And then you’re on an advanced node and you can do 1.5 billion transistors in the same area, and now you stack it and now you have three billion transistors. So it compounds, totally.

Vik: Yeah. So the whole tau scaling thing is not an “I will replace EUV technology and leapfrog around you without the right tools.” It is a temporary measure, where yes, you can bump up the performance of silicon with this technique. But if the people who are EUV-enabled do start doing the same thing — and they will, because that’s how the industry works, they’re not going to sit down and not do something about it — then the gap widens. It doesn’t narrow. The gap widens. That’s a good thing.

Austin: Yes. And maybe to make the point yet a third time — if, after Huawei’s big tau scaling announcement, someone came to their silicon manufacturer, whoever that is, and said, would you like EUV as well? I’m sure Huawei would say, sounds great, let’s have that and tau scaling.

Vik: Yes, exactly. That’s what you do. That’s the logical thing to do. So absolutely. So that’s the whole aspect about logic folding, and that is mostly the discussion that is going on here.

The Other Tau Knobs: Memory and Optics

Vik: But their paper actually talks about a few other dimensions that are at least worth mentioning. And that is basically what they call the unified bus for memory. Because they say, look, if you have all these different memory standards talking to each other, and then you have to have all these handshakes and converters and gearboxes and all of this stuff that adds latency, then you’re wasting cycles here. You’re wasting tau. Don’t waste tau. What we will do is have a universal language, which everything in the rack or the system or the data center — I don’t know, the earth, if you could — will all speak the same language, so that there’s no translations happening. And so that is one way to scale down the entire thing, the delay, and speed up stuff. It’s a very good one. I mean, I love it. It’s a very good thing to do anyway, regardless of whether you have EUV or not.

Austin: Totally. So isn’t that ultimately like — weren’t we trying to do that with RDMA and things, and just say, how do we make it so that GPUs can communicate with other GPUs to share their memory directly without so many handshakes? Was the industry already on this path? And does this just speed it up and say, hey, there’s more latency to get rid of?

Vik: Exactly. That’s the whole point. The industry has been there already. Again, this is not a new concept.

Austin: Just a different prioritization.

Vik: Yeah, exactly. When Jensen talks about extreme co-design, what do you think he’s thinking about? This is what he’s saying. Don’t just think about one thing, like memory in isolation, and work with your own standard, and when you try to plug it into a system it has to talk a different language, and now everybody’s like, can you convert this language to that language? Don’t do that. Let’s look at the whole thing as one picture, and then optimize everything for that system-level optimization. So this is the STCO argument — or you can call it extreme co-design, whatever fancy word you want to use. Tau scaling seems like the fanciest word I’ve heard yet.

Austin: Yeah, very good. Their marketing folks did great. So, you may have heard the term STCO — system technology co-optimization. Jensen took it up a notch with extreme co-design, and now Huawei’s trying to one-up with tau scaling. Which, I mean, it does sound pretty sweet.

Vik: It is pretty sweet. No — one other thing they want to save tau on is networking. Because they’re like, why don’t I just do near-packaged optics and eliminate DSPs from the entire system if possible? DSPs are terrible for latency. They are tau killers. DSP is the tau killer — like “fear is the mind killer” in Dune, if you’ve ever read the books. DSP is the tau killer. Because you have to wait for all the bits to arrive, and then you have to wait for the parity bits to come, and then the DSP looks at it and goes, are these bits correct? They’re not correct? Cool, then I have to correct for the error, and then it does all this computation. You need a leading-edge node to do this DSP stuff. Sucks power, sucks latency, and they want to do away with it.

They want to just get rid of DSPs, don’t use all this pluggable stuff. Use as close as you can to CPO, which is maybe near-packaged optics. Maybe you don’t — maybe they’ll try to package the optical engine right on top of this stack, logic, folded logic, whatever. I don’t know. But anyway, at least in the near term, they can put the optical engine as close as possible to the actual compute silicon.

Austin: Stack it up. Let’s go.

Vik: That’s one way to reduce cycles. So they’re looking at all of this stuff. Obviously you can do software optimizations, all that kind of stuff. So at the system level, they want to squeeze as much performance as possible — which is the only logical thing you do when you don’t have access to leading-edge silicon. What do you do? You do everything else. Exactly. That’s what tau scaling is.

Austin: Okay, gotcha. Yeah, of course, NPO and CPO make a ton of sense. Everything comes with trade-offs, though. So there’s the whole, like, does the supply chain support these things? Are they ready for it? Can they build it reliably? Do you have multiple sources? So I think it feels a little bit academic, in that, on one hand, anyone could sit down and look at a system and just say, what are all the different ways we could wave a magic wand to reduce tau? I don’t know if they talked about all the practical bits in the paper, or if this was more of just whiteboarding out where the bottlenecks are.

Takeaways: Bullish Packaging, EDA, and Multiphysics

Vik: Very high level. It is interesting that they have some silicon to show for it, which I love. But it’s also a lot of high-level, hand-wavy, equation-y stuff. It’s not very complicated equations — you can read the paper, it’s online, you can find it. It’s not a very complex paper, it’s very marketing-like, but it’s a good read. Because I think it’s another knob the industry hasn’t entirely paid attention to. I think we are getting there, and this is one of those signs. We realize that we need more speed, we realize co-packaged optics is coming along, we realize that memory bottlenecks are the biggest problem. It’s not compute flops, it’s memory and the interconnect that is really holding back everything now. And this is the next step — okay, how do we squeeze and make active silicon in CPUs, GPUs, or whatever that is, more dense? And the insane way to do it is start stacking them and hybrid bonding them. But this whole thing is insane. So what’s new? AI is insane to begin with. So what’s new?

Austin: Totally. Yes. Never before have we tried to co-optimize on such a grand scale and such a miniature scale. And so I do like looking at a different constraint to optimize around, up and down. So I guess, maybe final takeaways — what does this mean? And you kind of alluded to it before — what does this mean for everyone else, for TSMC, for ASML? Other than the fact that they’re not dead and EUV’s not going away, are there any other takeaways?

Vik: I don’t have too many, unless there is something that comes up that I haven’t thought about. But whatever I thought about, I already said. As a broad summary: I think going to stacking chips is a positive for ASML, because you need more machines to make more chips for the same product — you need to make two times as many wafers, which is a good thing. The other thing is that you will see most of the industry now starting to optimize across the entire stack. That’s already happening, nothing new about that. And then, I’m guessing that we will start seeing some activity around stacking up wafers. Maybe somebody’s going to try to use Intel Foveros and stack GPUs. I don’t know, that’s just a guess. But yeah, once Huawei talks about this logic folding idea, more people are going to do it. And that’s a good thing. Gotta try more complicated stuff — that’s how we move ahead.

Austin: Totally. I guess what’s coming to mind to me — obviously this is bullish advanced packaging, because it’s just more complicated connections. And then also maybe bullish EDA, and multiphysics.

Vik: Oh my God, great point. Actually, that’s a great takeaway. Yeah.

Austin: Yep. So we’re basically at time, so I won’t get into it too much, but really quick, at a high level — where I’m thinking is, okay, now this is a three-dimensional problem that involves thermals, it involves mechanical stress, it involves electricity, it involves optics potentially, if you’re talking near NPO/CPO. And so this becomes more and more of a challenge. This of course reminds me of, like, Synopsys/Ansys’s multiphysics engine — of just like, it’s going to be less and less of the silicon guy does this thing and the packaging guy does that thing and the thermals guy does that thing, but all of it needs to be brought together to figure out how do we stack logic on logic and remove the heat and still meet timing closure and still have reliability, and so on.

Vik: Yes. It is hard enough — EDA is a hard enough problem already, where we are on single-layer transistors, and you know how you scale them up to make the GPUs they are today. There’s a lot of advancement in the use of AI for EDA, and the whole EDA industry is actually very bullish right now, because you can basically sell licenses per agent rather than per person. And it can do a lot of stuff now. And what this adds is a level of complexity that we haven’t seen so far in the transistor world, when you start stacking entire wafers and running complete logic across two wafers stacked, or maybe four wafers stacked in the future. That’s crazy. So there’s going to be a lot of challenges there. And the paper actually does mention that this is a challenge. So that’s very much a good point to bring up.

Austin: Nice, cool. All right. Well, folks, with that, we hope you liked this episode. Check out, of course, our Substacks. Also go to semidoped.com — you can sign up for our free newsletter. If you like Vik and I and our takes, we try to give takes there every single day. And sometimes I come in later than Vik, so I just get to take a take on his take, and he doesn’t get to respond before I hit send. So we try to keep it lighthearted and fun, too. But thanks for listening, and we’ll catch you guys next time.

More importantly, and this is the downright most flattering thing that has ever happened to Semi Doped. Noam Hurwitz was inspired to start blogging again after listening to our Masterclass on Lithography episode, and decided to write an absolutely sick interactive article with dashboards and all the bells and whistles. You can move sliders around and see how everything changes!

Just one example of a dashboard that helps you understand wafer economics. Check out the whole post → Known Scaling Options for EUV Lithography

If you ever enjoy our content, reply/DM and let us know. Be like Noam.

Ok, now on to the today’s greatest hits! Good things await.

Be sure to check out the Semi Doped podcast on YouTube or your favorite podcast player!

TSMC reportedly eyes 15% 3nm price hike in 2H26, +5-10% in 2027 amid AI demand

TSMC is expected to raise 3nm wafer pricing by up to 15% in 2H26, with an additional 5-10% increase in 2027. Fab 18 monthly 3nm capacity climbed from ~130,000 wafers in early 2026 to 160,000-175,000 in Q2, but the report says AI demand growth continues to outpace the ramp.

3nm demand has flipped from smartphone-led to AI-led. Nvidia, AMD, Google, AWS, and other cloud customers are accelerating 3nm adoption for AI server refresh cycles and in-house ASIC programs. Institutional investors quoted in the report describe 3nm as the most stable mass-production node for AI chips, with better maturity than 2nm, which is still ramping yield. Per Liberty Times, Nvidia GPUs, Broadcom ASICs, and Marvell custom chips remain heavily dependent on TSMC. TrendForce estimates TSMC’s global foundry market share at 70.4% in 4Q25.

C.C. Wei is expected to address AI demand, advanced-node capacity, and overseas expansion at TSMC’s annual shareholder meeting on June 4. At a May 26 dinner with Jensen Huang, when asked whether TSMC could meet Nvidia’s capacity requirements, Wei replied, “we’re already working very hard” while making a zipper-across-the-mouth gesture. Huang referred to TSMC as “my good friends.” (TrendForce via Commercial Times)

Austin: TSMC can embrace a value-based pricing model, rather than a traditional “cost-plus” manufacturing pricing model. Which is a fancy way to say they have pricing power and a differentiated, premium product. We see this in margins, which are running way ahead of forecasted targets:

The question is, what is the true value of a 3nm wafer? It’s surely even more than what TSMC is asking even after price hikes. imo this is all a function of not enough supply…

Vik: Intel 18A capacity couldn’t come sooner. The world needs you Intel. Lip-Bu, we’re counting on you dude.

Marvell raises FY28 data center target by $1.5B to $16.5B as custom XPU “more than doubles” next year

Marvell reported Q1 FY27 net revenue of $2.41B, up 28% YoY, and guided Q2 to $2.67B ± 5%. Management raised the FY28 target by $1.5B to $16.5B and said custom silicon will more than double, split evenly across existing programs, XPU attach, and new tier-1 wins. All three buckets sized up since last quarter. CEO Matt Murphy held the $10B+ custom silicon goal against a $55B FY29 TAM.

CFO Willem Meintjes broke out scale-up optics (NPO/CPO) as a new ~$300M revenue line, calling it “Gen 1, ground zero.” The Polariton tuck-in adds plasmonic modulators with a claimed 10x bandwidth headroom on top of the Innovium scale-up switching base.

President Chris Koopmans said “everything that touches AI has been constrained since the beginning.” Marvell has put roughly $1B of supplier prepayments out this fiscal year and is now giving 5-year forecasts to lock capacity. Interconnect growth expectations have moved from 30% to 50% to 70%+ across three quarters. (Marvell IR)

Austin: How did I miss the Polariton acquisition!? Plasmonics! I had an amazing professor during undergrad who taught my “Electromagnetic Fields and Waves” course and his research focus was plasmonics. It was honestly over my head at the time, but I remember he was a fantastic artist and could draw amazing 3D images on the chalkboard (do they still have those anymore?)

Vik: Austin, you’re not reading my TWiC columns man. Scale-up optics is getting more real, with more InP orders coming in than the industry can handle. Polariton is Marvell bet for 3.2T networking.

Synopsys Q2 2026 +42% YoY, Elliott settles for a board seat

Synopsys reported Q2 revenue of $2.28B, up 42% YoY (quarter ended April). Shares fell 1.6% to $525.92 Wednesday and another 2.1% after the close. SNPS filed its 10-Q, Q2 transcript, and two 8-Ks the same day.

Synopsys also settled with Elliott Investment Management. Elliott managing partner Jesse Cohn joins the SNPS board on June 1, with a seat on the corporate governance and nominating committee, expanding the board to 11. Elliott agreed to standstill and voting commitments. Elliott disclosed a multibillion-dollar SNPS stake in March 2026, citing revenue growth that had trailed expectations despite the company’s EDA market lead.

“As an experienced board member, Jesse brings a uniquely differentiated perspective,” Aart de Geus, executive chair and founder of Synopsys, said in the statement Wednesday. (Bloomberg)

Austin: If you’re curious about the activist investor, Sassine addressed it well in the call during prepared remarks and the Q&A.

Dell raises forecasts on AI server demand

Dell lifted its fiscal 2027 forecasts, guiding to roughly $60 billion in AI server revenue and citing customer count above 5,000 across neocloud, sovereign, and enterprise buyers. Q1 AI server revenue came in at $16.1 billion, above the $14.6 billion quarterly run-rate implied by the full-year guide, with management attributing a back-half deceleration to supply constraints on DRAM, NAND, and CPUs rather than demand. COO Jeff Clarke said customer discussions now span three to five years, driven by access to supply. Shares rose about 38% in after-hours trading following the report. (Reuters)

Vik: Damn, first goes up 30%+, then again another 30%. IN THE SAME WEEK!

Quick Hits

• Foxconn projects 10,000 CPO switch trays in 2026 (@jukan05)

• BYD debuted an in-house smart-driving chip that the Chinese automaker described as the country’s most powerful, marking the company’s first proprietary silicon for advanced driver-assistance systems. (Bloomberg Tech)

• EXTOLL and Chip Interfaces unveiled what they call the industry’s first UCIe IP solution for GlobalFoundries FDX technology, enabling chiplet integration on FD-SOI nodes. (GlobalFoundries)

• Nvidia Research detailed advances moving robotics from simulation to real-world deployment, pushing generalizable embodied autonomy across its Isaac and GR00T robotics stack. (Nvidia News)

• Cerebras requires 24 systems and roughly $24M capex to run a single deep coding model at max context, supporting only 256 concurrent users per cluster. (X (@SemiAnalysis_))

Key Data

How much money a $20/mo makes for the model provider, depends on how much of your quota you use. So Anthropic revenue going to the moon means people got an AI sub, but haven’t figured out how to use it yet? What happens when they do?

Time to dive in.

Be sure to check out the Semi Doped podcast on YouTube or your favorite podcast player!

FuriosaAI lines up Broadcom for a 2nm, multi-die, HBM4-class inference accelerator

South Korean AI chip startup FuriosaAI is teaming up with Broadcom to build its third-generation accelerator.

The new design moves Furiosa’s TCP architecture into a multi-die system. It will use a 2nm compute die, HBM4/4E memory, several silicon dies in one package, and Broadcom’s Ethernet and PCIe technology for fast, rack-scale networking. Sampling is expected in the first half of 2028.

FuriosaAI was founded in 2017, raised about $115M across four funding rounds, and reportedly looking for another $300M to $500M before a planned IPO. They turned down an $800M buyout offer from Meta in March 2024 to stay independent. The first-gen RNGD (180W, PCIe, built on TSMC 5nm) is in mass production, and the second-gen chip is also in mass production at TSMC.

CEO June Paik said combining Broadcom’s infrastructure strengths with Furiosa’s architecture and software lets them deliver a full system rather than just a chip.

(Data Center Dynamics)

Peking University publishes a 3D EDA prototype tuned for Huawei’s LogicFolding

One day after Huawei revealed its Tau (τ) Scaling Law and LogicFolding architecture (covered in yesterday’s brief), Peking University’s School of Integrated Circuits announced a prototype EDA tool built to support LogicFolding-style chip designs. EDA tools are the software used to design chips.

The tool uses a “true-3D” method. Instead of designing flat 2D layers and stacking them, it treats a multilayer chip as one single structure from the start. On open-source industry-grade designs, it claims a 30% cut in total wire length, along with better performance and thermal behavior.

(SCMP)

Cognition raises $1B at $26B as Devin’s ARR jumps 13x in a year — inference demand made visible

Cognition AI just raised over $1B in a new round at a $26B valuation. That valuation is more than double its September 2025 round, and the company has now raised over $2.5B in total.

Its main product is Devin, an AI coding agent. Internally, Devin now writes more than 90% of Cognition’s own code. Devin’s revenue has jumped fast:

• $37M ARR in May 2025

• $492M ARR now, about a 13x jump in 12 months

• Goal of passing $1B ARR by the end of 2026

CEO Scott Wu said the new funding lets the company stay independent and keep operating on its own. On model strategy, he said that as the model layer gets more competitive, using a mix of models works better than relying on just one. Cognition runs a blend of its own models plus OpenAI and Anthropic.

(Bloomberg)

Quick Hits

• Snowflake is riding the AI data + agentic AI wave hard. They announced a massive $6 billion, multi-year strategic deal with AWS to supercharge enterprise agentic AI adoption. up >30%. (snowflake)

• Ayar Labs detailed a production-ready optically connected rack design for AI scale-up, targeting rack-scale systems like Nvidia and AMD’s 72-GPU configurations. (Ayar Labs)

  

• Epiwafer and substrate maker IQE of Cardiff, Wales, UK has completed its fundraising, yielding total subscription proceeds of £81m. (semiconductor-today)

• XFAB is getting pumped up by semi trader on X. Stock up 70-80% in one day. Proceeds to drop after. (bloomberg)

Key Data

We have a full episode coming up on the Semi Doped podcast this week about Huawei’s Tau Scaling and LogicFolding where we discuss thermal issues. Turns out Huawei is putting a micropump in Kirin fir cooling. Insane!

Google’s Coral Board

Look at this cute board for running AI on the edge. Available this summer, after Google I/O 2026. (via Google Gemma)

Let’s get into it!

Be sure to check out the Semi Doped podcast on YouTube or your favorite podcast player!

Micron, SK Hynix Reach $1 Trillion Valuation

Micron Technology and SK Hynix each surpassed $1 trillion in market capitalization, joining Samsung Electronics to make all three major memory chipmakers members of the trillion-dollar club. The gains were driven by surging demand for high-bandwidth memory used in AI data centers, which has tightened supply and lifted chip prices. Micron’s milestone drew public backing from both President Trump and Wall Street, according to Barron’s. Investor appetite for the sector extended to Asia’s leveraged products: a 2x Leveraged SK Hynix ETF listed in Hong Kong has attracted more than $1.3 billion in year-to-date inflows, pushing its assets to a record $8.0 billion.

Vik: Market cap 10x-ed in 1 year. ‘Nuff said.

Austin: Micron employee RSUs. ‘Nuff said.

Infineon raises power semiconductor prices

Infineon issued a second round of price increases for its power semiconductor products, sending the notice on May 26 with the new prices taking effect July 1. The move follows an earlier hike announced in February that took effect April 1. The increases cover Infineon’s power chip lineup, a segment used in applications ranging from automotive to data center power delivery. The back-to-back adjustments come amid reports of rising demand across the power semiconductor sector.

Translation

#Update: Infineon issued the second round of price increase notice on May 26. The previous round of price adjustment was the price increase notice released in February, implemented on April 1. This round's price increase notice was released on May 26 and will be implemented on July 1. The two rounds of price increases indicate strong demand in the power semiconductor industry, and the upward cycle of the industry has arrived.

Vik: Power Semi is here. 🚀

Austin: Memory is hot. Power is hot. CPUs are hot. GPUs are not? Poor GPUs, they generate all the intelligence and get no love. 😅

Semtech tops estimates, begins CopperEdge shipments

Semtech reported a fiscal-quarter beat and raised its outlook, driven by accelerating data-center revenue. The company began shipping its CopperEdge active copper cable product to a U.S. hyperscaler and said its 1.6T FiberEdge product is entering revenue, with the larger ramp weighted to the second half of the year. Management also pointed to growing traction for its LPO and LRO optical interconnect products and offered guidance commentary extending to fiscal 2028.

Vik: I looked into Semtech’s CopperEdge in quite some depth, and they are way ahead on ACCs. They cofounded the MSA, have named hyperscaler wins at Meta with cable partners, and another unknown CSP whose orders are flowing in. I have a deep dive published this week with all the nitty gritty details about the entire ACC industry, including Semtech. Check it out!

Vik's Newsletter

How Rack Power Density Is Opening a New Market for Active Copper

The discussion around interconnects, whether copper or optical, usually revolves around two factors and the trade offs around them: reach and data rate. As data rates rise, reach gets shorter and vice versa. As a result, networking is crudely divided into scale-up and scale-out domains restricting the former to within a single rack, and the latter to between racks…

Read more

14 days ago · 49 likes · Vikram Sekar

Quick Hits

• LightSpeed Photonics is targeting AI data centers with 400-Gbps near-packaged optical interconnects designed to move data between servers more efficiently. (EE Times)

• Cerebras confirmed its next-generation CS4 wafer-scale engine stays on 5nm, citing flattened SRAM scaling that makes a 3nm migration offer little practical benefit. (X (@SemiAnalysis_))

• Nvidia positioned its Vera CPU for agentic AI, touting fast cores, high memory bandwidth and sustained throughput for AI-factory workloads against rival server CPUs. (Nvidia News)

• Omni-Path, the high-speed interconnect nearly killed by Intel and spun off years ago, is being revived by a systems integrator for AI clusters. (X (@DanielNenni))

• Copper supply crunch is lifting component costs as tight upstream copper-concentrate supply keeps prices elevated despite rising exchange inventories, amid surging AI hardware demand. (X (@jukan05))

Key Data

But optical comms have sent soaring 150% this year.

Funny

LOL. Jensen dragging down my S&P index fund investments. Get on it dude.

Austin: Just wait for physical AI my dudes. Nvidia set to ride that S-curve. See my recent interview with Nvidia’s Deepu Talla:

Chipstrat

An Interview with Nvidia's Deepu Talla About Physical AI and Robotics

The industrial business of the future runs on fleets of agents. Some are digital (LLMs), some are embodied (robots), some are humans, and all need orchestration. Most people understand physical AI is here and coming, but most aren’t experiencing it yet and don’t yet have a feel for what makes it work or where it actually runs. So I sat down with Deepu Talla, VP and GM of Robotics and Edge AI at Nvidia, on what’s actually changed at the edge, what hasn’t, and what the path looks like from here…

Listen now

14 days ago · 16 likes · Austin Lyons

Be sure to check out the Semi Doped podcast on YouTube or your favorite podcast player!

SK hynix unveils iHBM in-package cooling

SK hynix introduced “iHBM,” a high-bandwidth memory design that embeds cooling elements directly inside the HBM package to manage heat in AI processors. The company said the structural approach lowers thermal resistance by 30% compared with conventional packaging. SK hynix described the integrated cooling as a way to address heat management at the package level rather than relying solely on external cooling systems. (prnewswire)

Vik: I can’t believe they called it an integrated cooling element (ICE) 😭 — interestingly, the D2D PHY that does all the comms stuff between the HBM and SoC generates the most heat. Moving all those parallel lanes of data is no easy task. And this ICE block is kept on top of the PHY to cool it. Thermal resistance drops by 30%. Expect it in HBM5.

Austin: Will Micron and Samsung have this too? Or are we starting to see some differentiation? I’m always trying to understand if there’s true differentiation between HBM providers or if a bit any vendor is undifferentiated.

Qualcomm lands ByteDance as launch customer for AI data center ASICs

Qualcomm reached a deal with ByteDance to supply chips for AI data centers, per Bloomberg. ByteDance is set to procure “millions” of Qualcomm-built ASICs to support its Doubao AI agent software. The chips are fabbed by TSMC and fall within US export-control compute thresholds, allowing ByteDance to source without tripping restrictions. ByteDance recently raised its AI infrastructure budget 25% to 200 billion yuan (~$29.4B) per SCMP. Qualcomm shares rose as much as 8.3% to a new intraday record on the report. CEO Cristiano Amon had previously hinted at “engagement” with unnamed customers on the post-earnings call last month (Bloomberg)

Austin: One detail buried in the piece was “This deal will help ByteDance turn an already-completed in-house chip design into a semiconductor that’s ready for production, another person familiar with the matter said.”

Qualcomm is acting as the ASIC design-and-implementation partner here?

OpenRouter raises $113M led by CapitalG at $1.3B valuation as weekly token volume hits 25 trillion**

OpenRouter, the AI model marketplace founded three years ago, raised $113 million led by CapitalG (Alphabet’s investment arm) at a roughly $1.3 billion valuation per a person familiar with the round cited by The New York Times, more than double its prior round. CEO Alex Atallah pitched the company as the “Stripe for AI models” — a single access point fronting 400+ models so customers aren’t locked into one provider. OpenRouter says it now processes 25 trillion tokens per week, up from 5 trillion six months ago. The most-used models on the platform over the past week were the open-source DeepSeek and Tencent models, followed by Anthropic’s Claude 4.7 Opus. Other investors in the round include the VC arms of Nvidia, ServiceNow, MongoDB, Snowflake, and Databricks, plus existing backers Andreessen Horowitz and Menlo Ventures. (NYT DealBook)

Austin: I use OpenRouter personally, so thought this was interesting. 5T → 25T tokens/week in six months… that was from like last November/Dec until now… makes sense! Agents! I am personally also trying to reduce cloud token usage and am instead running AI locally on my “agent computer”, Framework AMD Ryzen Max+ 395. More on that side project coming soon.

Quick Hits

• Schneider Electric expects its India data center business to outpace core growth, driven by the AI-fueled buildout of computing capacity. (Reuters)

• Xiaomi is pouring resources into AI, in-house chips and EVs, building open-source models and custom silicon to future-proof its hardware empire across product lines. (SCMP)

• AI server makers report component shortages so severe that GPU and CPU suppliers now verify every part is available before shipping systems. (X (@dnystedt))

Key Data

Intel EMIB Video

Cool video to watch if you want to visualize what EMIB actually does.

We’re here to take you beyond the spin.

Be sure to check out the Semi Doped podcast on YouTube or your favorite podcast player!

Huawei unveils logic-folding chip architecture

Huawei unveiled a chip architecture it calls “logic folding,” presented Monday by He Tingbo, chair of the Huawei Scientist Committee and head of its semiconductor business, alongside a new “Tau (τ) Scaling Law.” The company said high-end chips built on the approach could reach transistor density equivalent to a 1.4-nanometre (14-angstrom) process by 2031, without cutting-edge EUV lithography. The design relies on 3D stacking and hybrid bonding of logic and SRAM dies. Huawei framed the method as a way to narrow its gap with TSMC and Samsung amid US export sanctions, and said a Kirin smartphone chip launching this fall would use the technology. (Reuters)

We think there is too much hype around this new “scaling law” and is essentially what Jensen has been referring to as “extreme co-design” all along.

Zephyr_z9 on X calls out what the real news is here — hybrid bonding to stack logic chips.

CPU shortage is now worse than the memory shortage

Intel is pushing PC and notebook makers in the US, China, and Taiwan onto its 18A node (Panther Lake and Wildcat Lake), simply because 18A has better supply than the older nodes. Intel 7 is severely constrained, and Intel is steering those chips toward higher-margin server and industrial work where margins run about 20% higher than consumer. The leverage is real: one executive ordered 100 Intel 7 CPUs, received 30, was forced to take 10 of them as 18A, and was told that refusing the 18A units meant losing them to a competitor.

Adopting 18A isn’t free either, since it forces costly redesigns with premium displays and other higher-end components to justify the pricier chip, and verification takes at least three months. The punchline from the PC makers themselves: the CPU crunch is now worse than the memory shortage, because you can dial down memory specs but a PC can’t ship without a CPU.

Austin: I think this is fairly old news; Intel has long been saying they are trying to get off Intel 10/7 as I wrote about back in January. Intel’s CFO said they were trying to get rid of old inventory way back in Oct 2025 on the Q325 call… way before agentic AI took off

“Capacity constraints, especially on Intel 10 and Intel 7 limited our ability to fully meet demand in Q3 for both data center and client products… shortage is pretty much across our business, I would say. We are definitely tight on Intel 10 and 7. Obviously, we’re not looking to build more capacity there. And so as we get more demand, we’re constrained. In some ways, we’re living off of inventory.”

I’m wondering who is trying to order 100 Intel 7 CPUs, and why?

Micron taps TSMC for HBM4E base die

Micron will use TSMC to manufacture the base die for its HBM4E memory, marking the first time the company has outsourced base die production after relying on internal manufacturing through the HBM4 generation, according to SemiAnalysis analyst SK Kundojjala. HBM4E is set to ramp in calendar 2027, with an initial JEDEC-standard version followed by custom variants. The product will be Micron’s first HBM generation built on its 1-gamma process node, though the company already uses 1-gamma for LPDDR and DDR5. Both the standard and custom HBM4E versions will rely on TSMC for the base die.

Austin: From the Q126 call in December, CEO Sanjay Mehrotra said it was using a DRAM process for the base logic die:

“Our HBM4 uses advanced CMOS and advanced metallization process technologies on the base logic die and DRAM core dies, which are designed and manufactured in-house. This, along with our unique HBM design, packaging, and test capability, enables Micron’s industry-leading performance and low power leadership.”

Meanwhile, competitors Hynix and Samsung already use for logic base die from HBM4 onward. Micron has constantly had to answer for this to investors. It seems they have to no longer.

Quick Hits

Hiring & Layoffs

• TSMC employees threaten Samsung-style strikes over rumored bonus cuts, despite the company reporting a 58% profit jump, raising tension over compensation policy. (source)

Key Data

Austin: I see why frontier intelligence captures all the value. What happens if the next model doesn’t unlock such a massive jump in intelligence? I guess we are moving to a harness moat anyway?

Funny

Jensen literally creating bathroom graffiti now. This. has. got. to. stop.

Nearly three decades later, the same chemist — now at a Danish institute — faced an occupying force known for confiscating symbols of intellectual dissent. He concealed the Nobel Prize gold medals of two German physicists by dissolving them in a three-to-one mixture of hydrochloric and nitric acids. The orange solution sat openly on a laboratory shelf throughout the occupation. After liberation, he precipitated the gold, forwarded it to Stockholm, and both medals were recast.

The chemist co-discovered a metallic element at the same Danish institute, alongside a Dutch physicist, in 1923. Its oxide — with a dielectric constant roughly six times that of the silicon dioxide it replaced — enabled continued transistor scaling below the gate oxide tunneling limit, first appearing in production silicon at the 45nm node in 2007.

The element’s name is the direct Latinization of the city where it was discovered — a city whose name, in the language of its inhabitants, translates as “merchants’ harbor.”

Name the chemist and the element. Bonus points if you can name the Nobel laureates who the chemist helped.

“Merchants' harbor" = Kobenhavn = Copenhagen. Hafnia is the Latin for Copenhagen.

SPOILER ALERT: ANSWER BELOW

Aside: Magnetron sounds too close to Megatron. Now I’m worried my microwave is a Decepticon and is coming to get me.

A magnetron throws out microwaves at ~2,450 MHz. Water molecules are polar, so they flip back and forth trying to line up with that oscillating field billions of times a second, and all that molecular friction shows up as heat. The microwave does not cook “from the inside out” (a myth that started right here, with this exact discovery). It penetrates a few centimeters and excites the water in that layer directly, instead of heating the surface and waiting for it to conduct inward the way your oven does.

Some people say it was a PayDay bar, but nobody fully agrees. Most accounts say a plain chocolate bar; Spencer’s own grandson insisted it was a peanut cluster bar (he gave them to the squirrels outside the lab), which is the better version because peanuts and caramel melt at a much higher temperature than chocolate.

Spencer did what any curious engineer would do and aimed the tube at food. First came popcorn kernels, which popped across the lab floor; popcorn was the very first thing he microwaved on purpose, and it is still one of the most common things we microwave today. In another experiment, an egg was placed in a tea kettle, and the magnetron was placed directly above it. The result was the egg exploding in the face of one of his co-workers, who was looking in the kettle to observe. Spencer then created the first true microwave oven by attaching a high-density electromagnetic field generator to an enclosed metal box. The magnetron emitted microwaves into the metal box blocking any escape and allowing for controlled and safe experimentation. He then placed various food items in the box, while observing the effects and monitoring temperatures. There are no credible primary sources that verify this story.

Raytheon saw the gold mine. They filed the patent on October 8, 1945, ran an internal naming contest, and the winning entry combined “radar” and “range” into the Radarange. The first commercial unit shipped in 1947 and went to a Cleveland restaurant. It was a monster: nearly 6 feet tall, 750 pounds, and around $3,000 (north of $50,000 today). The 3 kW magnetron ran so hot the unit needed its own plumbing line for water cooling. This was not an appliance; it was industrial equipment for restaurants, ships, and military kitchens.

It took twenty years to shrink. In 1967, Amana (a Raytheon subsidiary by then) released the first countertop Radarange for $495 — still pricey, but finally something you could put on a kitchen counter. By 1975, Americans were buying more microwaves than gas ranges, and today the thing sits in roughly 90% of US homes.

For kicking off a multi-billion-dollar global appliance category, Raytheon paid Spencer their standard reward for any employee patent: a flat $2 and no royalties. He did fine anyway, retiring with around 300 patents on the strength of a fifth-grade education. MIT’s take on him was that the trained scientist knows in advance what won’t work, while Percy simply didn’t know what couldn’t be done, so he kept cutting and fitting and trying until something did.

One last thing, because this is Semi Doped. The magnetron at the center of this story is a vacuum tube, pre-semiconductor technology, and it never left. The microwave humming in your kitchen tonight is still driven by a magnetron, which makes it one of the last working vacuum tubes most people still own. A piece of 1940s radar hardware, quietly outliving the entire transistor revolution it helped kick off. Like the chicken and the T-Rex.

This podcast is lightly edited for clarity.

The Cost Problem

Austin: Hello everyone, and welcome to another Semi Doped podcast. I’m Austin Lyons with Chipstrat, and with me is Vik Sekar from Vik’s Newsletter. Hey Vik, what’s going on, man?

Vik: Yeah, not that much. Other than everybody’s panicked about the 13F from that Situational Awareness hedge fund, and there was a sell-off in optics and everybody freaked out. I’m like, what’s going on? First of all, I still don’t really know what a 13F is. I guess a hedge fund has to report some holdings that they hold, and what they sell and what they bought. Something like that.

Leopold Aschenbrenner — is that how you pronounce his name? Sorry if I got that wrong, I have no idea. It’s too many syllables. I guess he made a lot of money and converted a few million into a billion or something. And then everybody is following him for the latest stock tips. And when everybody looks at his 13F, they panic and there’s this whole sell-off. Apparently he shorted optics and shorted AMD, Intel, and sold it. I don’t know.

So everything is down in the semi market because of some hedge fund thingy. This is what’s happening. It’s funny.

Austin: I mean, so if I’m him, I’d wake up and look and go, wow, I can buy a few puts, because on this 13F — I don’t think it talks about the size of his puts or anything. So he can just buy a few puts at some point, drive the price down. Could he use that to then buy at that (depressed) price? That’s market manipulation, but in their hand, people are trading on public data and on vibes. He could throw people off his trail, right? Just buy a tiny amount of puts in everything and you wouldn’t know what he’s investing in.

Vik: Yeah, I don’t know. I don’t think Leopold listens to this podcast — but if you do, just let us know. Maybe you can come explain to us what a 13F is, because I don’t know about you, man, I have no idea what all this stuff is. So I’m happy to learn from the best.

Austin: Yes, Leopold, you’re welcome anytime. All right, so today we’re going to talk lithography. I thought it would be really interesting to talk about the economic challenges of lithography, modern EUV lithography especially, because ultimately incentives drive outcomes, and there are challenges with the increasing costs of lithography, the increasing costs of fabs.

And you start to see TSMC can afford the next process node, and Intel and Samsung are trying to stay in the race, or be in the race. There aren’t that many other competitors. And from afar, if you’re a semi-tourist, as they like to say on X, you might say, hey, TSMC is crushing it, why aren’t more people in this game? And of course, as you start to unpack it, you realize that costs are a barrier to entry.

And so you start pulling on the thread and you ask, well, what costs? And one of those major contributors to the capex needed to participate is modern EUV. So what do you think — should we talk EUV?

Vik: Yeah, that’s a great topic for today. I think it ties in tangentially to what’s happening to the market today, and why people think we are not on an unconstrained trajectory upwards. And this basically stems from the recent Gavin Baker interview that I put in one of our Semi Doped Daily updates on Substack. So if anybody is not subscribed to the Substack, I recommend it. It’s free. You can go get subscribed — semidope.com.

The idea that Gavin floated in that interview was: we are not in a bubble, because TSMC is basically holding back the entire industry by not creating enough chips for everybody, by controlling their level of capex spend on tools that require DUV and EUV. And most famously, I think TSMC is not pro-EUV. They think the tools are too expensive, and they want to stay on DUV with multi-patterning as far as they can manage to. And we’ll talk about what DUV with multi-patterning means in this episode.

This is where we are right now. Tools cost a lot. I think an EUV machine costs something to the tune of $400 million. And that’s just one machine. You need to run many of them to produce the chips at the scale we need, and that scale is continuously increasing. So it really comes down to: is EUV the only way forward? And then there’s Hyper NA EUV, which is extreme — I don’t even know if those are in production yet. I don’t think so. But those are going to cost close to a billion dollars. That’s insane.

Austin: Yes, totally. So we’ll unpack all this for everyone — what’s DUV, what’s EUV, why does it cost so much? That’s what this episode’s all about. A lithography masterclass, hopefully to set the stage for future conversations around lithography and some of the startups that are out there.

And actually, I just saw ASML shared a roadmap. I think imec had a conference — it’s going on right now, the ITF World conference — and ASML showed some of their roadmap and how they think they’re going to be able to bring the cost per exposure down. It would be nice to unpack this, but before we get to all those nitty-gritty details, we want to educate our listeners on some of the fundamentals. So let me throw out some numbers.

Inside the Clean Room

Vik: Hold on, I want to set one thing for Austin, before Austin. Most of this stuff, Austin is actually the expert, because he actually spent time working on this kind of lithography stuff in a clean room, which is something I can’t say I’ve done. I’ve measured wafers and measured transistors, that kind of stuff. I’ve handled completed silicon wafers, but I’ve never actually done lithography myself, and you have. So this is a cool thing. You can tell us a little bit more, rather than just what you can read on the internet. It’s interesting what it looks like inside a clean room. I’m excited to hear.

Austin: Yes, yes. Well, thank you for mentioning that. So when I was in grad school, I worked at the University of Illinois Urbana-Champaign, doing research as a research assistant, making graphene-based transistors. I was in a lab with Professor Eric Pop. He’s at Stanford now, and he studies 2D materials. People on our team were studying carbon nanotubes, and then I got to work in graphene.

So yes, I got to be in a clean room with silicon wafers — etching, depositing, doing lithography. And in fact, I even got to do E-beam lithography, because we were trying to make very precise, one-off little nano-electronic systems. It didn’t matter that the throughput of E-beam is really low. We’re not going to talk about E-beam lithography much here, but it’s a cool thing that I got to experience.

When I first started, we were mechanically exfoliating graphene, which means we were taking tape — we get graphite, layers of pencil lead essentially, and then we take literally clear tape and stick it on top of the graphite and pull it off, and then take it under a microscope and look, and you can figure out how many layers of graphene you have there. So I’d just scan around, doing some of this stuff in a bunny suit, and then going back into the lab and moving this thing around, just thinking, what am I doing with my life? I’m trying to find single-layer graphene. That’s what I’m doing.

But of course, once you find single-layer graphene, then we’d pattern the transistors right there on it, and take measurements and publish it, because it was a hard thing to do. So we kind of had an advantage that we knew how to do it. I won’t talk too much more. We eventually did chemical vapor deposition to create graphene using copper foil essentially, and then we could grow graphene — it wasn’t as pristine and pure, but it was more scalable. Anyway, good memories. I spent a lot of time there.

Vik: Amazing stuff. I bet it was a great experience. At the time, it’s probably frustrating as all hell, as all research is, but then looking back at it, it’s like, I don’t mind doing that again now. At least going into a clean room and pottering around would be nice.

Austin: Totally, man. It was challenging in that you couldn’t just do the research — you had to do a lot of exploration to figure out how to even make the thing before you could actually measure it and do the research. So yes, it was frustrating at the time, because you’d spend a whole day and then get to the end and be like, that didn’t work. But looking back now, it’s like, how fun was that? How much intellectual freedom there was. Your research professor says, hey, go make this thing, and you’re like, well, I guess I’ve got to read and experiment and try to figure out how to make it, and then measure it, and then see if our hypothesis was correct.

Vik: Yes, yes. Nice. Okay, now we’re good. We hit carbon nanotubes already — research that’s never made it out of the lab. You spent time doing that. Awesome. Now let’s talk about stuff we can actually make.

Rock’s Law and the Price of a Fab

Austin: Okay, so let’s talk about — have you heard of Rock’s Law, by the way?

Vik: I have not.

Austin: Okay, so this is a quote-unquote law, just like Moore’s Law. It’s really an observation, named after Arthur Rock. He was an early investor in Intel, maybe one of the founders of the venture capital industry, if you will. But the observation was that the cost of a semiconductor fab doubles every four years.

So it gets more and more expensive. Now this is interesting — this is related to Moore’s Law, where Moore’s Law said that the number of transistors in an integrated circuit doubles every two years. And so if the cost of a fab doubles every four years, that’s slower than the number of transistors doubling every two years. What that means is that Moore’s Law is really an economic statement that says: for roughly the same price, we can get more transistors per die area, per chip, per unit area over time. And that’s really what drove the industry — that economic realization that for the same dollars, you could get more compute over time.

We are getting to the point where the cost of fabs is getting so high that we’ve seen, decades ago really, Moore’s Law — the number of transistors doubling — shrinking for physical reasons, but also from an economic perspective, the cost of transistors flatlining and potentially even the cost per transistor coming up. And again, the question is what’s driving that fundamental change to some of these important economic scaling laws that we’ve seen for decades. And lithography is a big contributor. Like you said, low NA EUV tools used to cost around $250 million, now high NA’s coming out around $400 million, give or take. These numbers change over time, and it probably depends per customer. You can back some of this stuff out of ASML’s reports, because they don’t sell many of these per year.

But anyway, yes, the rumored Hyper NA, which would be a future tool, could cost anywhere from $600 to $800 million potentially — if the Strait of Hormuz stays closed, maybe a billion dollars, because that’s driving everything up. So which means lithography, all of these tools — like you said, we’ll get into it — you might need 15 tools to open up a new fab. I think I’d seen some CNBC coverage where it said that Intel’s 18A fab in Arizona, Fab 52, needed 15 EUV machines. So imagine that: half a billion dollars a pop, and you need 15 of them. That is no joke. And that’s why a brand-new fab costs on the order of $20, $30 billion.

So I just wanted to quickly paint the picture of the enormous capex cost to just build one new fab to try to stay in this race. And of course that ultimately means the cost per wafer will have to go up too, because you can only do so many wafer starts per month — say tens of thousands of wafer starts per month, or a hundred thousand — and you need to amortize the cost of all those tools over that fixed number of wafers.

Vik: Okay, cool. So let me back up a little bit and quickly frame it in a way that I usually process things. One of the biggest problems of modern lithography is cost. And that primarily stems from having to make smaller and smaller transistors. We have gone from deep ultraviolet, which is what we’ll refer to as DUV, to eventually extreme ultraviolet, which is what EUV stands for. Then within EUV, we have several levels of numerical aperture. I think we should define what that is next, so that we have all these basic terms in place.

So we have low numerical aperture, or low NA EUV, and high NA EUV, and then Hyper NA EUV. The higher you go, from low to high to hyper, the smaller the transistors you can make. So basically, the higher the numerical aperture, the smaller the transistors, the smaller the feature sizes you can make.

Now, regardless of whether you choose a deep ultraviolet or an extreme ultraviolet machine, you’re going to need at least 10 or 20 of them in a fab. And if each of them costs, I don’t know, half a billion dollars, and you want to put in 10 of them, you’re spending $5 billion on just these EUV machines. Not only that, you have to put in a whole lot of other infrastructure, like cooling. The clean rooms are difficult, because you have to have HVAC systems that pull all of the dust particles out of the air. Based on how many dust particles you can find per unit volume, these clean rooms have different classifications — you’ve got class 1, class 10, class 100. I think the higher the number, the more particles per cubic volume of air.

So all of this stuff takes an enormous amount of money and time to build. Actually, here’s another point. If you look at TSMC’s construction of their fabs, critical machines are suspended on pistons. Entire factory floors are suspended on pistons so that it’s immune to earthquakes and stuff. So it is very expensive to build a fab.

And it takes years. It could take three to five years. So this is why we can’t simply add chip capacity willy-nilly.

Austin: Totally, totally. And not only that — if you haven’t seen a fab, I’d encourage people to figure out how to get on a fab tour if they can somehow. I know it’s very difficult. But Vik wants to go. I actually had the good fortune recently of getting to go to Intel’s Fab 52 and tour it. So not only do you not want the machines to move around even a tiny bit from earthquakes, but even from passing traffic and stuff.

Vik: I’ve never been in one.

Austin: Of course, we’re making transistors on the atomic scale, nanometer scale, and so you don’t want any sort of mechanical wiggling and movement. Also, these EUV machines have big power sources, and the light source — a lot of that actually goes in the sub-fab floor. So there’s a floor beneath the main floor where the tool sits, and they have all this equipment underneath it. And then of course there’s a floor above it, and you’ve got to flow all that air through.

So I also wanted to illustrate that it’s not just like data centers, where you find some real estate, slap a building up, throw some racks in and you’re good. Even from a construction and HVAC perspective, building a fab is no joke.

Vik: And it goes beyond that, because if you look at Intel fabs and the way they’ve built them in the past, they had this “copy exactly” method, which means they copy exactly. This is not something they mess around with. They use similar plumbing. I’ve heard that they even use the same brand of paint, because they do not want anything to go wrong. If small things happen and change the way a fab functions, you can’t get the yield up. And if you can’t get the yield up after spending $20 billion, you can’t make enough wafers, which means you can’t sell them and make a profit.

So Intel decided to copy exactly. And that actually slowed a lot of stuff down for them — that’s a different story. But really, that’s how difficult it is to build a fab. I mean, that’s insane.

DUV and the Art of Multi-Patterning

Austin: Totally. All right, going back — you mentioned DUV and EUV, so let’s tell listeners a little bit. Back in the DUV days, the light source that was used had a wavelength that eventually made its way to 193 nanometers.

And zooming out even further: lithography, at the end of the day, for those who don’t know — I think everyone probably does these days, because ASML is an awesome company and everyone wants to invest, or has invested, and so at a high level understands what lithography is. But we’re talking about ultimately being able to expose light to, in quotes, “draw” the shape of transistors, or the shape of areas that you want to etch away — you leave parts of the transistor but etch away other parts of the surface of the chip.

And so ultimately, to make transistors smaller and smaller, you need to make the wavelength of light smaller and smaller. But there’s also something we can get into, which is the numerical aperture — the mirrors you talked about, changing the numerical aperture. But just focusing on making the wavelength of light smaller: the canonical example here is, if you’re writing with a Sharpie, you’re going to draw fat lines. And if you can write with a fine-tip marker, a fine-tip pen, you can make a lot thinner lines, and you could draw smaller, precision features. So that’s what the industry was trying to go to, from DUV, deep ultraviolet lithography, to EUV, which uses 13.5 nanometer light. So ultimately you’re going an order of magnitude smaller, from the fat marker down to the fine-tip pen.

Vik: Yeah. So this whole relationship you mentioned, where you want a smaller wavelength of light but a higher numerical aperture — this is governed by what is known as the Rayleigh criterion, which means that the smallest dimension you can make on a wafer is literally proportional to the wavelength, but inversely proportional to the numerical aperture.

There is also a constant factor here that’s often called K1, which we won’t get into, but think of it as another knob you can use, by designing the masks that selectively allow light or don’t allow light in regions. They do all kinds of tricks on those masks to improve this proportionality factor K1. We won’t get into it, but these are the factors. So there’s a bunch of tricks, then there’s the wavelength, and then there’s the numerical aperture.

So the smaller the wavelength you go, the better. And to Austin’s point, deep ultraviolet lithography most famously ended at what is called argon fluoride lithography — is that right? — at 193 nanometers. And then there was a quantum leap down to 13.5 nanometers with EUV, with extreme ultraviolet. So that’s a big change. That’s more than a 10X change. And going down another 10X hasn’t happened yet, but we will get to how that can happen at the end of this episode. But yes, keep going. Let’s go.

Austin: Okay, let’s talk about DUV for a second. Do you want to explain where the 193 nanometer light comes from, with argon fluoride?

Vik: There was a whole evolution to that as well. It’s not like we just landed there right when we started lithography. In the 1980s, it was mostly what was called i-line lithography, which had a wavelength of 365 nanometers. Then over the years, people realized, wait, we’ve got to make this better. And then they came up with krypton fluoride lithography, KrF lithography, that went to 248 nanometers. So just by changing the kind of light source you’re shining through, and the wavelength of the light source, you could get better features.

So going through the 90s, you could have 248 nanometers. That evolved to argon fluoride lithography, where they went to 193 nanometers. And that was pretty cool. But then that lasted all the way through the 2000s, let’s say. They kind of ran out of light sources. They did try some other light sources along the way, but they didn’t really work out, for various reasons. And then they were kind of stuck with argon fluoride for a while.

But then they thought about it: how do we improve numerical aperture? Somehow we have to improve it. And the answer was extreme, actually. It’s amazing. If you come to think of the history of lithography, it’s insane. Some smart guy came up with the idea and said, how about we put water on the wafer? Let’s just put water on it. You want to put water? So yeah, that’s literally what they did. They put extremely pure water on top of the wafer, and then put the light through the water onto the wafer. And that came to be called immersion lithography. So that actually helped scale transistors further, just by putting water on the wafer. It’s insane, right?

The history of lithography is amazing. I wanted to tell you the way it all started — I don’t know if you know this. The way it all started, in the early days — I forget the name of this guy, look out on Semi Doped, we’ll have a poll post on this thing — the main idea of making masks and making transistors smaller came about because this guy, I think he was working for TI, was looking at a microscope, and he was like, wait a minute, if I can flip the microscope over and shine light from the other side, it gets smaller, right? Everybody knows, you look the wrong way at these things, stuff gets smaller. So he’s like, this is it, I’m going to turn the microscope upside down and shine light through the wrong end and everything gets smaller. And that’s how all of lithography came about — the optics in lithography came about — because this one guy had the idea to turn the microscope upside down.

So that’s how it all started. And then we’ve been continuously going down the path of these various laser materials, down to putting immersion lithography with water, and ultimately coming down to extreme ultraviolet lithography, which is an engineering feat that is an achievement for humankind. That’s how big it is. We’ll talk about it too.

Austin: Yes, yes. So, Vik, you make some interesting points here — optical lithography, it’s all about light sources and about the optics, about the mirrors, about how you bend the light. When you talk about the guy having the insight of, when I look at a microscope, it makes small things seem bigger, so if I flip that lens, I can make big things seem smaller — what an amazing way to take a big mask and make it smaller to be patterned.

And then ultimately, when you’re talking about moving through various materials and unlocking smaller wavelengths, we’re talking about lasers. These are light sources to shine through the optics that we’ve been talking about. And ultimately, the industry was just playing with what different materials can laser at shorter and shorter wavelengths.

And this leads me to — we got to argon fluoride, 193 nanometer, and the industry sort of stuck for a while, waiting to figure out the next way of unlocking even shorter wavelengths, ultimately EUV as we know it today, which we’ll get into. But in the meantime, the industry came up with this nice trick called multi-patterning. And I thought I’d explain it really quickly, because there are also economic trade-offs to multi-patterning.

So multi-patterning is ultimately about — the question is, how do you draw features smaller than a single wavelength? Let’s come up with an analogy. Let’s say you’re drawing the lines on a football field, an American football field — the end zone, zero yard line, 10 yard line, 20 yard line, and so on. And maybe you have a machine that is, I don’t know, really fat, and it can only draw a line every 10 yards. The 10 yard line, the 20.

Well, then maybe the coach comes to you and says, hey, we also need markers at the 5 yard line and the 15 yard line and the 25 yard line. And at first you’re like, well, wait, my machine can only print them every 10 yards, how am I going to possibly do that? And then some clever person comes up and says, oh, well, just draw 10, 20, 30, 40, and then go back to the start and scooch it over five yards and draw 5, 15, 25, 35.

It takes twice as many steps, but instead of having to get a new machine that can now print every five yards — zero, five, 10, 15, 20 — you just draw them every 10 yards, and then you offset by five yards and draw 5, 15, 25. So when you zoom out and you’re done, you’re like, wait a minute, now I’ve drawn lines every five yards, even though I didn’t have to get a new machine.

And that’s an analogy for what’s going on in multi-patterning, which is drawing features in step one that are only spaced at the distance you can comfortably make, and then coming back in with another step and drawing a second set of features and just offsetting it. The amazing thing is, with a trick like multi-patterning, you can unlock shorter dimensions between the drawn features. But of course, the economic cost to this is it takes twice as many steps — it decreases your throughput by half.

Vik: I love the analogy, by the way. That’s a super cool way to understand it. So what you’re saying is basically you can do a coarse etch, scooch it over, do a coarse etch again, and what you’re left with is a fine etch. Because now, by scooching over somewhere in between the last two etches, you can get a finer spot. And if I remember right, this terminology is called litho-etch, litho-etch. So you’ll see this as LELE, right? Is this the same thing I’m talking about?

Austin: Yes, exactly. You nailed it.

Vik: Okay, cool, cool. Now, I think people have taken this to more than two levels of litho-etch, right? They’ve gone to triple patterning and even quad patterning, which is all cool and all, because now you’re stuck with two problems. One, it becomes increasingly difficult to even align masks between the yard lines. When you had to align the mask at the 15 yard line, it was okay, whatever, it was between 10 and 20. But now you want to align it at 12, 14, 16, 18, and you’re like, okay, that’s the problem.

The second problem is you’re going to run through four different quad-patterning steps, and each one takes the same time, so it kind of scales linearly. Now it takes four times as much time to make that one lithography step. And I’m not sure how many levels this can be applied to with quad patterning, but making a transistor isn’t like one etching step, or one lithography step — there are many of them. And if you have to quad-pattern on multiple steps, it adds up a whole lot of time and the throughput decreases, which means the cost per transistor goes up, or you don’t get enough amortization of the original $20 billion investment. And now we’re at a crossroads here.

What “Two Nanometers” Really Means

Austin: Yes, yes. And case in point — I know SMIC, which is the fab in China, they’re not allowed to get EUV. And so they were able to take DUV and use tricks like quad patterning to get to seven-nanometer-class and then five-nanometer-class transistors.

Which I wanted to point out, by the way, because it’s related to lithography: nowadays, when we’re talking about making transistors, it’s no longer just two-dimensional transistors, it’s really three-dimensional transistors — FinFETs, that have these fins. We should find some pictures, and people, go Google it — and RibbonFETs. So now you’ve got these three-dimensional shapes. And making a transistor actually takes on the order of 60 or 70 or 80 steps, because you have to pattern and etch and deposit material over and over and over to build up this 3D-shaped transistor.

So there’s also kind of a marketing thing — the semiconductor tourists, for lack of a better word, which just means you’re new to semis. It’s no shade. I was a semi-tourist at one point.

Vik: Welcome — everybody is welcome into Semi-Land. Love you. Very inclusive.

Austin: That’s what this podcast exists for. Yeah, exactly. When a fab says we make two-nanometer transistors, or 1.8-nanometer transistors, it’s the smallest dimension. This critical dimension — like we talked about before, the distance between any two really close lines — is not two nanometers. It used to be, back when they were 90 nanometers and 180 nanometers and 45 nanometers, that was a lot closer. But it became a marketing term. So actually, something that’s called two nanometers, the smallest dimension may still be on the order of 30 nanometers.

Vik: Yeah, yeah. So it’s not actually two, but that’s what we call it now, because it’s somehow the equivalent of two.

Austin: Yeah, correct, correct. It’s the equivalent, when you think about transistor density and whatnot. But I will say it’s important, because naturally, when we say 13.5 nanometer EUV wavelength, someone might go, well, that’s still way too big to draw two-nanometer lines. But it’s not, exactly.

So you might think, if we went from big fat marker DUV to fine-tip Sharpie EUV, we must not have to multi-pattern anymore, right? And actually, your intuition is correct — from a resolution perspective, we don’t have to. But from a yield perspective, the industry can still need to rely on some multi-patterning. There’s a really nice graphic from Fred Chen’s Substack — he wrote a nice article on it, we’ll link to it in the show notes.

Ultimately, we are getting so small that when you’re shining very short wavelength light at a certain dose, there’s only so many photons that are hitting there, and you can only control them so precisely. You’ve got resist chemistry going on, and there might be some — ideally there’s not — but there might be some impurities or even dopants in the way. And so you end up getting this stochastic nature. When you draw with the Sharpie, you don’t actually get a very fine line. If you zoom in, there’s some little dots around the edges and stuff. Think of it maybe like spraying with a spray paint can or something. It’s not a perfect line.

Vik: I’m looking at the picture, and I was thinking of spray paint, exactly. You always nail these analogies, and I was like, I’m going to nail this spray-paint analogy.

Austin: Yes. So ultimately, what they do is, you might draw with the spray paint twice to get a better-defined line, especially as you’re starting to go into three dimensions. So I just wanted to throw that in there — now we’ve jumped up to these $300 million, $400 million EUV tools, but the throughput isn’t immediately solved, because there’s still some multi-patterning that may have to happen. And there are other things about the power of the light source and the dose, but we won’t get into those now, because we’re really starting to get into the weeds.

But okay, what do you say we jump in? Should we talk about high NA next? Or do you have anything else to add here that’s useful at a high level?

Making 13.5nm Light

Vik: I think we should conclude — before we talk about NA, we should talk about how we can generate light at 13.5 nanometers in EUV. We mentioned that these were laser light sources based on argon fluoride lasers. But it’s quite different when it comes down to 13.5 nanometer EUV. And that is where the hardest innovation actually was, holding back the industry from going to this for a very long time.

Fundamentally — in a simple way, it’s far more complex than I’m explaining it — but in the simplest way, it is basically tin droplets that fall through a chamber. You hit it with laser light, and it gets activated, and then you hit it again with the laser light. Remember, you have to hit a falling tin droplet that’s about 50 micron in size, twice, as it falls through this chamber. The second time, it gives you an explosion of 13.5 nanometer light. That keeps happening, precisely.

ASML has an awesome video on their website where you can see these tin droplets falling. It’s an animation, you can’t really see this thing — but these droplets are falling and these laser sources are continuously hitting the droplets, and you see these explosions of EUV light. That then goes through mirrors — it goes through like 13 different mirrors — because it has to be focused ultimately onto the wafer. And then it lands on the wafer, where it hits a mask, and then it selectively exposes or doesn’t expose stuff.

One of the big problems is that you went through all this trouble to get extreme ultraviolet light by shooting lasers, but then you reflected it through so many mirrors, and at each reflection you lose some power. Less than a single-digit percentage of the actual generated EUV power actually gets to the wafer. It’s a big loss because of these mirrors. There’s literally no way around it, or so we think. But that’s what I wanted to talk about, because now that we’ve finished talking about how lasers and light sources work, numerical aperture is a good transition to get into right now.

Austin: Yes, this is good. I almost skipped over EUV entirely, at least low-NA EUV. So it’s a good introduction. We were stuck at DUV, we tried multi-patterning, and in the meantime the industry was trying to work on EUV. And as Vik talked about, ultimately we’re trying to find a light source that has a much shorter wavelength. Work had been done that showed with tin, you could basically induce a plasma — that’s why you hit it twice, ultimately — and that plasma would generate 13.5 nanometer wavelength light.

But there were a lot of engineering challenges and optics challenges around: great, yes, when we’re under vacuum we can generate a plasma and it will emit this really short wavelength light, but how do we ultimately harvest all that light? How do we reflect it back, and aim it with mirrors? Ultimately you need to gather this light, because it’s just going to shoot in any direction, presumably, from the tin droplets, and you need to gather it all. And then you need to get it to where it needs to be, to where the mask is ultimately. And while you’re doing that, you’re trying to focus all the light. And like Vik said, there are a lot of losses every time light hits a mirror — it’s not going to all bounce perfectly, exactly in the direction you want, there’s going to be some scattering and some loss.

So ultimately you end up losing so much light in the process that you don’t have enough to expose the photoresist. And so the question the industry was working on for a long time is not only how do we make all this work repeatedly, but also how do we increase the light source, so that ultimately, by the time we harvest all this light and get it exactly where we need it, focused all the way down, we still have enough to actually expose the photoresist and draw the transistor.

So that’s why we were stuck at DUV for a while — because this is an amazing engineering feat. Read the book Focus, by Martin something, I don’t remember his last name, but it’s about ASML. What’s really interesting is it talks about the entire supply chain and all the co-innovation needed — for example, famously, from Zeiss with their mirrors. So it’s no joke to even build the laser-produced plasma light source, but then you have all the optics.

And of course there’s something called a scanner. We won’t talk about it a ton, but ultimately, when you’re patterning the mask, you don’t want to just pattern one — you don’t pattern one die or one chip. Like we talked about before, it’s like a checkerboard pattern on a big dinner plate. You need to draw these transistors for every checkerboard square. So you need mechatronics that move everything around so you can repeatedly print all of this. There’s a ton of engineering to make this even possible.

Vik: Yeah, that’s insane. 13.5 nanometer EUV is an incredible feat of engineering. We are here today because ASML took 20 years to develop this.

And the whole question of how ASML ended up with this is another interesting one, because this technology was actually developed in the United States. At some point it was sold to ASML. And at that time, the United States government didn’t come in and say, no, this is critical technology, we want to hold it. The US government has blocked many such things before, including protecting 5G technology — they’ve done all of this stuff. Even now there’s so much export control. This was before the day of export control. We, from the United States, handed over the keys to the kingdom to ASML a few decades ago.

And kudos to them, they spent 20 years developing it. There’s an enormous supply chain that goes into ASML’s machines that all needs to come together to make this work. So it’s built on a massive amount of effort. But I just wanted to point out that this was actually US technology at one point.

High NA and the Limits of Mirrors

Austin: Totally, that’s a great history lesson. We should write more about that history sometime. Okay, so we’re running long, but let me blow through this. It’s an engineering marvel to get 13.5 nanometer light, but we want to make transistors smaller. What do we do?

Like we talked about with the Rayleigh criterion, you ultimately have two big knobs you can turn. One is the wavelength of light — but if you’re like, dude, we spent so long to get here, we’re not just going to turn that all of a sudden, 13.5 was hard enough. The other knob is the numerical aperture, which ultimately has to do with the size of mirrors. And so that’s where we get into high NA and extreme NA, or whatever it was called, Hyper NA.

But maybe really quick: the industry’s trying to move from 0.33 numerical aperture, low NA, to 0.55, high NA, which makes features on the order of 1.5 to 1.7 times smaller possible. But there’s a catch — there’s always a catch in engineering, there’s always trade-offs. You need bigger mirrors. When you have bigger mirrors, you’ve got these steeper light angles as they bounce in, and you have something called anamorphic optics that come into play. And I won’t get way into how that works and what that means, other than to say you ultimately end up only being able to pattern an area that’s half the size of what you could with low NA. They call this the half field.

So basically now, instead of your $250 million machine printing an area, you’ve got a $400 million machine printing half the area. Of course, that sounds horrible. Now you’re telling me — okay, Mr. Salesman, I just bought a $250 million machine from you, and now you say I need not only your $400 million machine, but I need two of them. That’s crazy.

ASML has done a ton of amazing engineering, where they’ve said, yes, we can only do a smaller size, but what if we speed up the scanner and the mechatronics to go even faster to make up for it? So it’s like, sure, the area is going to be smaller, but we’re just going to move that thing around the wafer even faster. And again, ASML has all these amazing videos on YouTube where they show how fast they’re accelerating and moving this stuff. It’s crazy. It’s like fighter-jet-style acceleration, but with nanometer precision, moving things perfectly around, stopping and reversing. It’s crazy that it all works.

But again, things are expensive. There are more trade-offs. There’s a lot more innovation that needed to happen. And ultimately, even with the proposed Hyper NA, even bigger mirrors, there are even more trade-offs, even with stuff like photoresist. So I’ll just leave it at that — we won’t dive into high NA or Hyper NA — but just trying to illustrate that not only are there economic challenges, there are also engineering challenges, and presumably reliability challenges.

So we’ll leave you with this. The question is, instead of the mirrors, could we make the wavelength smaller? How could we make the wavelength smaller?

Vik: Yeah, I want to add one more thing about the mirrors — that’s an engineering challenge — but then we’re going to talk about how to go even smaller wavelength.

These mirrors are not simple. It seems like, what’s the big deal going from low NA? You just have to make a bigger mirror. Make a bigger mirror, what’s the problem? These are not ordinary mirrors, because they are actually made up of 40 or 50 alternating layers of very thin molybdenum and silicon. They’re layered like this, and it is insanely smooth.

I read this book, Chip War by Chris Miller. It’s a good book, I recommend it. It talks to a lot of history, and a lot of what I’ve said here is from that book. And I have a quote here from that book. It says, “if the mirrors in the EUV system were scaled to the size of Germany, their biggest irregularities would be a tenth of a millimeter.” Think about that. Think about how flat those mirrors are. We’re going to put up a picture here and you’ll see how smooth it is. It is very difficult to even hold this thing — I feel like I would only want to breathe on it. I don’t know, they probably have protective gear.

But making bigger mirrors isn’t easy. It is an incredible engineering feat to make irregularities a tenth of a millimeter when the mirror scale is the size of Germany. That’s really flat, right? That’s a very smooth surface. So it’s not simple that we can go from a 0.55 NA, which is high NA, to like 0.75 next year. We’re used to the incredible pace of AI. Everybody’s like, oh, what’s the big deal, we can go to 3.2T, 6.4T, 12.8T networking, no problem. When are we going to get there, two years, three years, what’s the time frame? No, no, this stuff is difficult. You cannot make a mirror that easily.

So that’s where we are right now. And now the question is, what’s next? A machine costs a billion dollars, and now you tell me there’s only half field, and now I need two billion-dollar machines. The economics is exploding. Something is going wrong. And so this is where we have new ideas, to go where no human has gone before.

The Startups Rethinking Lithography

Austin: Totally. Okay, transitioning here. People will say, you could never compete with ASML. It took the industry so long to figure out this 13.5 nanometer light, and they have a supply chain — they have a relationship with Zeiss, the only company in the world that can make these perfect mirrors. Why would Zeiss sell their mirrors to you, dumb startup? Of course they’re not, because they don’t want to make ASML mad. And so now you’re going to have to go get another company to be the next ASML, or the next Zeiss. It’s never going to happen, right?

And so some startups are saying, okay, hold the phone. Let’s forget all that. Let’s just think simple, from first principles. Could we get a smaller wavelength of light? How do we tackle the optics? How do we tackle the integration, the mechatronics, all that stuff?

So one startup, xLight, out of California — and I think Pat Gelsinger is on their board now, maybe he’s the chairman of the board or something. What they’re trying to do is they’re saying, what if we use free electron lasers as the light source? So we’ll replace LPP, laser-produced plasma — that’s the tin droplet, shooting it with the laser machine gun and all the magic that happens. A free electron laser, by the way — think of it as accelerating electrons to near light speed. You’ve got these undulators that wiggle them, and you can get this coherent light. It can ultimately scale down to one nanometer, sub-one-nanometer.

But what if we start by using this new technology, but still producing 13.5 nanometer light, so that it can plug into existing ASML scanners and ASML optics? And by the way, FEL has a much higher total power, so what you could ultimately do is have a higher dose, which is better for yield. But actually, what xLight’s trying to do is say, what if we use one free electron laser, and we can actually split the beam and feed many EUV scanners? So they’re ultimately trying to decouple the light source from the scanner. What if you could buy 10 scanners and feed them with one light source?

Or maybe they’d have to have two light sources, one as a backup in case one doesn’t work, but you get the gist. So that’s the approach they’re trying to take — what if we build one massive free electron laser next to the fab and pipe the light into all of your ASML scanners? You can amortize the cost of your FEL across all those scanners. There will be some integration, but we’re not going to ask everyone to change the optics, the photoresists — we’re not going to ask anyone else in the industry to change. We’re just going to decouple the light source.

Vik: That’s fancy. Yeah, I haven’t looked into xLight, so I’m actually learning on the fly right now. That’s amazing. One of the things you can do with a laser source that has a higher output power is — tell me if I’m wrong — if you can get more light onto a wafer, the throughput actually increases, doesn’t it? Not only yield, the throughput goes up.

Austin: Correct, correct, correct. The throughput, exactly. If you only need a small flashlight to shine on something, and now you’ve got really powerful light, you could get the same amount of light by taking your really powerful light and shining it for less long, exposing it for less long.

Vik: How many photons get in?

Austin: Exactly. So therefore you can increase the throughput. But you could say, okay, well, the yield maybe isn’t that great the way the industry is doing it now. So we’ll shine it for just a little bit longer than we need to, and you’ll get even more extra photons. So you can have a higher dose, but ultimately have both better yield and better throughput.

Vik: So who would be the end customer of xLight? Would it be ASML?

Austin: No, it would be the fab. The fab would be buying. And the crazy thing — I wrote about it on Chipstrat, you can go check it out — the business model here is ultimately selling light, sort of like a utility, “photons as a service.”

You might ask, okay, why would TSMC go build an FEL from some startup, and then have to rejigger and work with ASML to say, we don’t want your LPP light sources, we just want your scanner part? That seems like a lot of risk and a lot of effort for TSMC — and a lot of capex, by the way.

What if xLight came in and said, we will pay to build this utility right next to your fab, just like you get electricity delivered, just like you get water delivered, and even just like you buy gas? These fabs will buy inputs like gas in this consumption-based way. Let us build the FEL, the light source, and then we will just charge you for what you consume. So it’s on our books, we take the capex hit, and then we’ll just charge you. If you want to spin up three scanners, fine, we’ll feed you three scanners. Now, of course, xLight ultimately wants you to spin up as many scanners as possible, but there’s a way that xLight can take a lot of the risk and do a lot of the upfront investment, and then just sell light to TSMC over time.

And by the way, once they build that relationship, not only could they sell you 13.5 nanometer light, but maybe for a premium later, once you and the industry are ready, they could sell you one nanometer light. So it’s a very interesting business model.

Vik: So the optics and stuff still comes from ASML, but then you’ve got this free electron laser sitting on premises at TSMC, just supplying light. They count the number of photons you use and charge you for it? Is that the whole business model?

Austin: Yep, presumably. How they do that — how they track how much light you’re consuming — would also be very interesting to know. But exactly, it’s like your electricity bill at the end of the month is going to be your light bill. Your light for lithography.

Vik: Amazing. So what other ways are there to make one-nanometer-wavelength light?

Austin: All right, one more that we’ll hit on today. Substrate is another startup. They’re also in California, in San Francisco, and they are throwing out the playbook and taking a different approach. Instead of FELs, they’re saying, hey, what if we use X-ray lithography?

Historically, X-rays were generated by big synchrotrons — football-stadium-size particle accelerators, essentially. There’s precedent there: again, you speed up these particles, they get super high energy, super high energy means really short wavelength, and you can ultimately control it and use it as a light source. The industry has actually explored using X-rays as a light source. And again, if you Google “Chipstrat substrate” you’ll find this, I wrote about the history — IBM did a ton of work. A lot of this early research happening in the United States. IBM did a ton of work here to see, could this be a path forward for the industry? And they actually made a synchrotron, or an X-ray light source, that fit on a truck. So it’s a bit of a myth that it has to be massive — they figured out a way to make it a lot smaller.

And this is the approach Substrate’s taking. I’d phrase it this way: IBM and a bunch of other people, back in the 80s and 90s, explored X-ray lithography, and it was a working prototype. It wasn’t economical yet, but a lot has changed in 30 years — not only about light sources, but with photoresists and optics and everything else it takes to build a light source and a scanner and do lithography. What if we went back and revisited from first principles, and took a stab at X-ray again, and said, hey, given all that we’ve learned in the last 30 years, could it now be economically possible to do lithography using particle-accelerator-based X-ray lithography?

Vik: Yeah, I wanted to step back one minute and quickly explain what a synchrotron is. The idea of a synchrotron is that you accelerate a charged particle in a ring — in a circle or an ellipse or something like that. And as the charged particle, which is continuously being accelerated, turns around and changes angle, it spits out X-rays as it turns around. That’s basically how a synchrotron works.

And typically, in the past, like you mentioned, these are really big installations. Particle accelerators tend to be really big, depending on what energy you have to accelerate them to. But I think the invention for making tabletop synchrotrons has been around 20, 30 years already. So it’s not something you really need a whole lot of space to do. That’s very important, because people shouldn’t be like, what do you mean? You need a football field, we don’t have that kind of space, so we can’t do X-ray lithography. No, I think it can be done in a smaller way.

But the one thing I learned when I wrote about this — it’s on my Substack too, about Substrate and X-ray lithography — is that it’s very difficult to actually focus X-rays. We spoke about the mirrors for EUV lithography, but you can’t do that for X-rays, because they go through things. You can’t reflect them. That’s a big problem. So the optics for X-rays is a challenge. It really is a challenge.

So one of the ways you can do this is what is called proximity printing. Like we mentioned earlier, the inverted-microscope approach means you could scale down a mask — you could put the mask on the big end of the microscope, and then the other end scales it down, let’s say five times. That’s called reductive printing, I forgot the exact term. Basically, you can reduce the magnification factor by a factor of five, because you’ve got this inverted-microscope approach. By the way, it came to me — the person who did that was Jay Lathrop, he’s the guy who came up with this idea. The name came to me later.

So you can’t do that with X-rays, because there’s no optics that works with them. You have to do proximity printing, which means you’ve got to make masks the same critical dimension as the stuff you’re patterning. So the masks are actually very fine. And for this purpose, the mask-making is significantly harder when you’re using X-ray lithography, because you don’t have the optics for them. So there are a whole lot of challenges that need to be solved. It’s not just, we’ve got X-rays now that go to one nanometer, so just swap out the LPP 13.5 nanometer source for a one-nanometer X-ray and then voila, you can print 0.1 nanometer gate-all-around transistors or whatever it is. It doesn’t work that way. Once you change the wavelength, everything changes.

And that’s where we are now. There’s this startup called Substrate that’s working on this. They made quite a splash some time back, because they feel that not only can they make smaller transistors and continue to scale Moore’s Law, but X-ray lithography can be significantly cheaper — you don’t need to spend $1 billion for an EUV machine anymore. Which means that most people, with far less capital investment — going back to the whole economics angle that we started with in this podcast — can make more fabs.

And then, if this technology is held within US soil this time, and not given away, maybe all of manufacturing will come back to US soil. If we can make X-rays work, and now we can own all of the supply chain required to make — well, I don’t think we can own the whole supply chain, but if we can at least make wafers on US soil and have so many fabs that we don’t rely on anybody else, that would really propel the chip-making industry like we have never seen before. So that is the case for making X-ray lithography on US soil.

Austin: Totally, man. There are so many implications. We have to do a full episode on this — hopefully we’ll talk to them.

First of all, it’s good that you point out there’s lots of engineering that has to happen, not only with the light source, but with the optics. And there are implications for the mask — how do you draw a mask at such small dimensions? Maybe it’s E-beam. There’s going to be a cost to that, right? So there are lots of technical questions to get answered.

But to your point, the implications are very profound. If in fact it can ultimately reduce the cost — hey, could GlobalFoundries make two-nanometer chips? Could Texas Instruments? Why not? So what are the implications, which I think is super interesting, of these legacy fabs, trailing-edge fabs, now being able to make even smaller transistors at the cost of maybe their trailing-edge nodes? Tons of implications.

What does that mean for fabless design companies, where you’re like, well, yeah, maybe we’d make our own chip, but that’s pretty expensive — I don’t know, probably we can’t amortize $100,000 per wafer, we only need five wafers or something. But what if all of a sudden, it was the cost of a 90-nanometer chip, where you can now buy wafers for $10,000 instead of $100,000, but get two-nanometer transistors? Crazy implications. And then, to your point, the geopolitical implications are fascinating too.

Vik: Ultimately — you know what will happen ultimately? What Jerry Sanders said: real men will have fabs again.

Austin: Totally, totally. Even that — why did every company at the start of semiconductors have a fab? Well, because ultimately, if you’re vertically integrated, you’re going to get a better product. If you can co-design across the fabrication — across the design and the fabrication — if you can design but also design for manufacturability, all in the same house, you’re just going to go faster, you’re going to build a better product.

But ultimately, the cost, because of Rock’s Law, got so big that people had to drop out, because they couldn’t afford a billion dollars for the next fab — $2 billion, $4 billion, $8 billion. Everyone has to drop out, because the GlobalFoundries or the TIs, they just can’t, they don’t have enough volume or high enough ASPs to amortize that cost. So it’s just dropping off.

But yes, in an ideal world, some of these players would still love to design and build their own chips. And of course, from a wafer-allocation perspective, you own your own destiny. There are so many amazing implications. I know everyone gets super hung up on, the technology is impossible, who dares think they can take on ASML and Zeiss and all that crap. But I’m more excited about all the positive implications that will happen, that will benefit all of us.

Vik: If you’ve been watching this on YouTube, you’ll notice that I’ve been drinking from this lens cup. So now that it’s over — I guess that’s our episode. We’ve spoken a lot about lithography. So let’s get on with it.

Austin: Totally. Okay, that’s it for today, everyone. Thanks for listening, thanks for hanging with us. We hope you’re enjoying Semi Doped. Please tell your friends about it, pass it along — if they want to learn about lithography, send this to them. Send us questions and comments on YouTube. Subscribe at semidope.com to our Substack that we’ve started. And thanks, as always, for joining us in this journey.

Be sure to check out the Semi Doped podcast on YouTube or your favorite podcast player!

US to fund nine quantum firms with $2B and take equity stakes

The US Commerce Department said it will award $2 billion in grants to nine quantum-computing companies, with the government taking a minority equity stake in each. IBM is set to receive $1 billion and said it will add $1 billion of its own cash to build what it calls the nation’s first specialized quantum chip manufacturing facility, housed in a new business that will take the government investment. GlobalFoundries is slated for $375 million; the remaining firms, including D-Wave Quantum, Rigetti Computing, Infleqtion, Atom Computing, PsiQuantum, and Quantinuum, are set for $100 million each, except startup Diraq at $38 million. The funding draws on the 2022 CHIPS and Science Act. In premarket trading, IBM and GlobalFoundries rose about 7%, while D-Wave, Rigetti, and Infleqtion gained 15% or more. (WSJ)

Austin: If quantum bubble becomes quantum reality, the US Government wants the technology to stay in the US of A.

Vik: Perhaps it is better for GF to focus on the ongoing battle for SiPho foundry dominance? Quantum seems pretty far out, but optics is here right now.

Anthropic projects $10.9B Q2 revenue and its first operating profit

Anthropic told investors it expects second-quarter revenue of $10.9 billion, a 130% jump that would more than double its $4.8 billion of first-quarter sales and deliver a $559 million operating profit, its first, according to figures reviewed by WSJ. The company disclosed the projections as part of a funding round likely to value it above OpenAI. Anthropic primarily runs on chips developed by Google and Amazon, which typically cost less than Nvidia’s, and said its compute spending fell to 56 cents per dollar of revenue this quarter from 71 cents in the first. It has signed a string of recent data-center deals, including with SpaceX, to expand capacity. The operating-profit figure includes model-training costs and excludes stock-based compensation. (WSJ)

Austin: WSJ implies Anthropic is driving computing costs down by using TPUs and Trainium and comparing to Nvidia’s GPU costs. That’s not the story imo; in fact, Anthropic is finally moving to using a lot of Nvidia GPUs as Jensen made clear on the earnings call. Rather, Anthropic is generating fewer tokens for “all you can eat” monthly plans and is instead allocating tokens to the consumption-based enterprise plans. That’s how you increase revenue per compute dollar (or decrease the cost to generate the revenue).

AMD pledges $10B+ across Taiwan, ramps Venice EPYC on TSMC N2

AMD announced more than $10 billion in investments across Taiwan’s ecosystem to expand advanced packaging capacity, accelerate AI infrastructure, and deepen collaboration with key partners including TSMC, per AMD’s press release. In a separate announcement, AMD said it has begun production ramp of the 6th Generation AMD EPYC “Venice” processor on TSMC 2nm (N2) process technology. (AMD-$10B Taiwan investment, AMD -Venice on N2)

Austin: This advanced packaging bit caught my eye, wafer and panel-based EFB (elevated fanout bridge):

• EFB ecosystem development: AMD is collaborating with Taiwan-based ASE and SPIL, as well as other industry partners, to develop and qualify next-generation wafer-based 2.5D bridge interconnect technology. EFB architecture increases interconnect bandwidth and improves power efficiency, supporting “Venice” CPUs.
  

• Panel-based innovation with PTI: AMD has achieved a major milestone with PTI by qualifying the industry’s first 2.5D panel-based EFB interconnect.

Quick Hits

Memory / Storage

• University of Tokyo researchers demonstrated a non-volatile spintronic memory device that can rewrite a magnetic state in 40 picoseconds (EE News Europe).

Inference architectures

• Researchers (NVIDIA+Groq) published “SHIP: SRAM-Based Huge Inference Pipelines for Fast LLM Serving,” documenting Groq’s first-generation public cloud architecture as the first large-scale SRAM-based LLM inference deployment serving hundreds of billions of tokens daily (Semiconductor Engineering).

• AMD detailed a $3,999 Ryzen AI Halo developer mini-PC and Ryzen AI Max PRO 400 series supporting up to 192GB of unified memory for local LLM inference (ServeTheHome — Halo, ServeTheHome — Max PRO 400).

Foundry / Packaging

• Daeduck Electronics will invest more than 800 billion won to simultaneously expand FC-CSP, FC-BGA, and AI substrate production capacity (The Elec).

Power / Energy

• Nebius signed Bloom Energy for up to 328MW of behind-the-meter solid-oxide fuel cells to power US AI data centers (Data Center Dynamics).

• Oregon’s PUC approved a new rate class under the POWER Act forcing 20MW+ data centers to fully cover grid infrastructure costs (Data Center Dynamics).

Labor / Capacity

• Samsung Electronics reached a tentative wage agreement with its largest union on May 20, postponing an 18-day general strike, with member vote May 22-27; the deal abolishes the 50% bonus cap and ties chip-division bonuses to 10.5% of operating profits (Data Center Dynamics, The Elec).

Economy

• Taiwan April export orders rose 48.1% YoY to $87.45 billion, the 15th consecutive month of growth (X — @dnystedt).

Key Data

Morgan Stanley’s table shows how value of power content per AI rack scales in the 800V high-voltage DC (HVDC) era that we are just about to enter. Bullish power.

Useful Tool

Genuinely useful tool that you can use to play around and to understand how different models consume kV cache → kvcache.ai